1. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan1 Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, Alabama 36849, USA

2. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan2 Outline Specifying a BIST problem Proposed method Spectral Analysis BIST implementation Results Fault Coverage Area Overhead Conclusion

3. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan3 Two Types of BIST methods Scan-based testing Advantages: High fault coverage Disadvantages: Area & delay overhead, yield loss, large vector size and testing times Non-scan based testing Advantages: Disadvantages of scan-based testing eliminated Disadvantages: Requires sequential ATPG  High test generation complexity and low fault coverages  Alleviated using DFT schemes Sequential ATPG-like vector generation in BIST environment Problem definition

4. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan4 Proposed Method Step 1: Spectral analysis Sequential vectors (ATPG or any other type) analyzed in the spectral domain Significant spectral components chosen for BIST implementation Step 2: BIST implementation Hardware synthesis of significant spectral components to generate ATPG-like vectors

5. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan5 Test vectors and bit-streams Sequential Circuit (CUT)..... Input 1 Input 2 Input 3 Input 4 Input 5 Input J Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 →........ Vector K → Outputs Time A bit-stream

6. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan6 Spectral Characterization of a Bit-Stream 1 1 1 1 1 -1 1 -1 1 1 -1 -1 1 -1 -1 1 1 1 1 1 -1 -1 -1 -1 1 -1 1 -1 -1 1 -1 1 1 1 -1 -1 -1 -1 1 1 1 -1 -1 1 -1 1 1 -1 H 8 = w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7 Walsh functions (order 8) Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream Walsh functions form the rows of a Hadamard matrix Example of Hadamard matrix of order 8 time

7. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan7 Analyzing Bit-Streams of ATPG vectors Spectral Analysis Vector 1 Vector 2. Input 1 Input 2. Sets of bit-streams of Input 2 input 2 set 1..... Bit stream Spectral coeffs. C(2,1) input 2 set 1 0s to -1s Time Set 1 Set j

8. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan8 Determining Significant Components Set 1.. Set J Component Spectrum Power Spectrum Averaging Averaged Spectrums For input i M significant components chosen Phases of significant components

9. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan9 Input Vector Holding Hold input vectors constant while applying system clock. Holding length related to sequential depth. Sequential depth: Maximum number of FFs on any path between PI and PO. Holding a vector constant for number of clock cycles equal to sequential depth propagates a fault through the activated sequential path[1]. Holding maps combinational ATPG onto acyclic sequential circuit [2]. However, all testable combinational ATPG faults not detected by holding [3]. [1] L. Nachman, K. Saluja, S. Upadyaya, and R. Reuse, “Random Pattern Testing for Sequential Circuits Revisited,” in Proc. Fault- Tolerant Computing Symp., pp. 44–52, June 1996. [2] H. B. Min and W. A. Rogers, “A Test Methodology for Finite State Machines using Partial Scan Design,” J. Electronic Testing: Theory and Applications, vol. 3, no. 2, pp. 127–137, 1992. [3] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, "Combinational Automatic Test Pattern Generation for Acyclic Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no.6, pp. 948-956, June 2005.

10. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan10 Holding and Weighted Random Patterns CircuitTotal No. of faults Number of faults detected 64k random vectors 64k weighted random vectors Without holding With holding Without holding With holding s298308269273 s820850414449744764 s14231515891121714491469 s14881486116113691443 s537846033222342432883537 s923469271268130512931303 s15850138635249627058476696 s38417311804087418548034949

11. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan11 To CUT BIST Architecture Weighted pseudo-random pattern generator Spectral component synthesizer Input 1 Input 2 Input 3 Hadamard Components 2 3 1 1 1 To CUT Randomizer Hadamard wave generator Clock divider and holding circuit System clock BIST clock Weighted pseudo-random bit-streams M-bit counter divides system clock frequency repeatedly by 2 and generates BIST clock N-bit counter with XOR gates SC 1 SC 2 SC 3 Weighted random bit-stream (W=0.5) Proportion: SC 1 = 0.5 SC 2 = 0.5 Proportion: SC 1 = 0.25 SC 2 = 0.25 SC 3 = 0.5 Cellular Automata Register with AND-OR gates Weighted random bit-stream (W = 0.25) Bit-stream of spectral component Noise inserted bit-stream System clock BIST clock

12. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan12 Hadamard BIST Results Circuit Total No. of faults Number of faults detected Flex Test ATPG 64k random vectors 64k weighted random vectors Hadamard BIST (64k vectors) Haar BIST 1 (64k vectors) s298308273 s820850793449764777710 s142315151443121714691468 s14881486144613691443 1441 s5378460335473424353736033609 s9234692715881305130317291413 s158501386373236270669668445888 s38417311801547241854949170204244 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Equal or more faults detected than ATPG in 5 / 8 circuits

13. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan13 Hadamard BIST Results Circuit Total No. of faults Number of faults detected Flex Test ATPG 64k random vectors 64k weighted random vectors Hadamard BIST (64k vectors) Haar BIST 1 (64k vectors) s298308273 s820850793449764777710 s142315151443121714691468 s14881486144613691443 1441 s5378460335473424353736033609 s9234692715881305130317291413 s158501386373236270669668445888 s38417311801547241854949170204244 Maximum faults detected in 6 / 8 circuits

14. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan14 Longer BIST Sequences Circuit FlexTestHadamard BIST Fault coverage (%) No. of vectors Fault coverage (%) at 64K vectors Fault coverage (%) at 128K vectors BIST vecs. for FlexTest ATPG cov. s29888.6415388.64 757 s82093.29112791.4191.88(!) s142395.25388296.90 22345 s148897.3173697.11 (!) s537877.0673978.2778.678984 s923422.921552824.9625.258835 s1585052.826168749.3752.15198061 s3841749.625511054.5963.0743240 ATPG fault coverage achieved in 6 / 8 circuits

15. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan15 Area Overhead Circuit No. of transistors in circuit Hadamard BISTHaar BIST 1 No. of transistors % Area overhead No. of transistors % Area overhead s298890908102.0283493.71 s82018961472 77.64161285.02 s142346241637 35.40155533.63 s148840061069 26.68107826.91 s5378128402342 18.24248719.37 s9234233562700 11.56255210.93 s15850436964908 11.23459510.52 s384171088083606 3.312135 1.96 1. S. K. Devanathan and M. L. Bushnell, “Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST,” in Proc. 20th International Conf. VLSI Design, 2007, pp. 485–491. Approximately similar area overheads

16. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan16 Conclusion Proposed a novel method for test generation for sequential circuit BIST Proposed unique circuits for mixing spectral components and noise Method detects equal or more faults than ATPG vectors in 6 out of 8 ISCAS’89 benchmark circuits Moderate area overhead compared to existing methods Proposed method is flexible and adaptable Any other suitable vectors can be used instead of ATPG vectors. Any compatible transform for binary bit-streams can be used for spectral analysis instead of Hadamard transform. BIST coverage limited by coverage of ATPG vectors DFT for sequential circuits to improve ATPG coverage

17. November 25Asian Test Symposium 2008, Nov 24-27, Sapporo, Japan17 Thank You! Any questions please ?