1. Design with Vivado IP Integrator

2. Complete IP & System Centric Design Flow
Vivado IP Integrator
Vivado RTL Integration
Vivado IP Catalog
Vivado HLS
Vivado now provides direct flows from all four design environments into and out of the Vivado IP catalog
System Generator for DSP

3. IP Integrator – Now full public access Enabling Reuse and Delivering Fully Functional IP Subsystems
IP Packager
Source (C, RTL, IP)
Simulation models
Documentation
Example Designs
Test bench
Standardized IP-XACT
IP Subsystem
Xilinx IP
3rd Party IP
User IP
Uses multiple plug-and-play forms of IP to implement functional subsystem
Includes software drivers and API
Accelerates integration and productivity
Slide 8: IPI
Time on foil: 2 mins
Speaker Notes: Introduction:
Vivido’s new IP Integrator builds on the foundation of Vivido’s extensible IP Catalog and stands based approach to packaging up IP.
Vivado Design Suite provides an extensible IP catalog, which can contain Xilinx, third-party, and intra-company IP that can be shared across a design team, division, or company. Vivado Design Suite leverages industry standards such as ARM®’s AXI interconnect and IP-XACT metadata when packaging IP. Now with IPI, Vivado Design Suite facilitates rapid development of smarter systems, which can include embedded, DSP, video, analog, networking, interface, building block, and connectivity IP consolidated into a hierarchical system and IP-centric view.
With open, industry IP standards, Vivado Design Suite enables third-party vendors to deliver their IP portfolios to developers, who can now integrate them with Vivado IPI. Users can also package their own RTL, or C/C++/SystemC and MATLAB®/Simulink® algorithms into the IP catalog using Vivado High-Level Synthesis (HLS) or System Generator for DSP with the Vivado IP packager.
Leveraging the extensible IP catalog, IPI provides automated IP subsystem generation. That then itself can be packaged for reuse.
Over 1,000 IPI customer designs generated as of September 2013
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4. Vivado IP Integrator: Platform Aware
Co-Optimized for platforms
Target platform aware
Supports All Programmable Zynq and 7 series kits
HPC
(J22)
LPC
(J2)
PCIE(P1)
Co-Optimized for silicon
IP aware automated AXI Interconnects for maximum performance or area
Automated interface, device driver & address map generation for Zynq and MicroBlaze

5. Vivado IP Integrator: Intelligent IP Integration
Correct-by-construction
Extensible IP repository
Real-time DRCs and parameter propagation/resolution
Designer Assistance
Hierarchy Support
System Hierarchy View
Interface Connections with Live DRCs
TCL Console
Extensible IP Catalog
Automated IP Subsystems
Block automation for rapid design creation
One click IP customization

6. Advanced GUI with Full TCL Support

7. Debug Support User marks signals or interfaces to debug
This automatically sets up waveforms in HDL simulator to view
Also specifies signals to debug in hardware

8. Working with Hierarchy
IPI supports arbitrary levels of hierarchy
Action available from the “right-click” menu
You can create an empty level of hierarchy or automatically move selected blocks

9. Working with Hierarchy
Diagram hierarchy can be cross-probed
Hierarchy is preserved during generation

10. Design Rule Checks (DRCs)
DRCs are run at multiple times
While making connections
By executing “Validate design”

11. Clock / Reset Management
Clock and resets are a special “type” in IP Integrator
You can cross-probe and view its frequency

12. Clock DRCs Interfaces have CLK_DOMAIN and FREQ_HZ properties
Validate design checks to ensure these are correct

13. Clock / Reset Management
See UG898 for more information on reset and clock topologies
MicroBlaze without MIG
MicroBlaze with MIG
Zynq without PL
Zynq with PL
Zynq with MIG in the PL
Design with MIG and Clocking Wizard

14. Configuring Zynq Designer Assistance shows in the green ribbon banner
The Zynq PS only shows in the IP catalog when a Zynq device is selected

15. Configuring Zynq

16. Configuring Zynq

17. Migrating from XPS to Vivado IP Integrator
There is no magical upgrade from XPS to IPI. However…
UG940 has a section on converting legacy EDK IP to IP Integrator cores

18. Migrating from XPS to Vivado IP Integrator
Copy the legacy EDK IP directory to a new location
Launch the Vivado IDE from this location
Select Manage IP from the Vivado IDE Getting Started page
Select the part and language preferences (this will show by default but can be disabled)
Launch the IP packager wizard from the pulldown menu Tools > Package IP
The IP packager will automatically scan the legacy EDK IP directory
Review the tabs and make changes as suggested below
Once you are satisfied with the changes in the Review and Package tab, select Archive IP. This action results in the generation of a <componenet_name>.zip which can be copied to your user IP repository and added to the Vivado IP catalog.

19. IP in Vivado vs CORE Generator (From UG896)
Vivado Design Suite IP are accessible in a single unified IP Catalog
Vivado Design Suite IP are delivered as HDL and are usable for both simulation and synthesis/implementation
Vivado Design Suite IP use the new Xilinx Design Constraints (XDC file) for physical and timing constraints which are applied automatically
In the Vivado Design Suite, a synthesis design checkpoint (.dcp file) replaces the .ngc file as the container for both the IP netlist and scoped constraints
In the Vivado Design Suite, each IP (.xci file) needs to be in its own directory (see the documentation on the Managed IP Flow and In Project Flow)
In Vivado Design Suite, you no longer use the XilinxCoreLib for simulation (unless using older IP) as each IP delivers its own simulation sources as an output product

20. Packaging IP for IP Integrator
The IP Packager is accessed from the Tools menu
You can package the current project or a specific directory

21. Packaging IP for IP Integrator
The IP Packager guides the user through the process of packaging an IP for Vivado
The final output is a single ZIP file for distribution

22. Packaging IP for IP Integrator / IP Management
To point Vivado to IP to be added to the library, right-click in the IP Catalog (Or Tools -> Project Settings… -> IP)
This could be user or 3rd party IP
Multiple IP locations can be specified
Network locations are acceptable : \\mycompanyserver\IP

23. Packaging IP for IP Integrator / IP Management

24. Packaging IP for IP Integrator
Now the IP is available in the Vivado IP Catalog

25. Packaging IP for IP Integrator
The IP has the same look and feel as all other Xilinx IP
Parameters can be customized

26. Using MIG in IP Integrator
Both Block and Connection Automation are available for supported boards

27. Using MIG in IP Integrator
See UG898 for more information

28. Using AXI_VDMA / AXI DMA in IP Integrator
Connection Automation is available for the AXI DMA and AXI VDMA
Use it to connect the DMA AXI_LITE interface to the Zynq GP0 interface or MicroBlaze M_AXI_DP

29. Simulation options for designs which include PS7
Xilinx includes a Zynq Bus Functional Model (BFM) with Vivado Design Suite (additional license required)
DS897 – Zynq-7000 Bus Functional Model
AR – Zynq-7000 BFM Example Design
TCL script to generate an example IP Integrator design and test bench

30. IPI Customer Material Available Today
UG 940 – Vivado Design Suite Tutorial (Zynq, SDK, MicroBlaze) -
New Zynq cross-trigger lab
New IP Packager lab, packaging a pCore
UG 898 – Vivado Design Suite User Guide (Zynq, SDK, MicroBlaze)
New chapter – Designing with MIG in a Zynq and MicroBlaze design
New chapter – Clocking and reset topologies in IPI
UG 994 – Designing with IP Subsystems User Guide
How to use IP Integrator (was a chapter in UG896)
UG 995 – Designing with IP Subsystems Tutorial
Lab – A processor less design with several peripherals (was a chapter in UG939)

31. Thank You