1. Parallel accelerator project Final presentation Summer 2008 Student Vitaly Zakharenko Supervisor Inna Rivkin Duration semester

2. System functionality Large picture ◦ Multiple signal sources share the same media. ◦ Each source produces a periodic pulse sequence in the media. ◦ Observer of the media senses superposed pulse sequences with the addition of noise. ◦ Preprocessor detects pulses in the signal and stores each pulse as pulse TOA (time of arrival). ◦ The pulse TOA array produced by the preprocessor is conveyed to the system. ◦ The system separates pulses into original signals (i.e. into periodic pulse sequences).

3. TOA1TOA2TOA3TOA4TOA5TOA6TOA7TOA8TOA9TOA10TOA11 TOA1TOA2TOA3TOA4TOA5TOA6TOA7TOA8TOA9 Missing pulse effect TOA1TOA2TOA3TOA4TOA5TOA6TOA7TOA8TOA9

4. System components Simulator On a PC constructs datagrams. Datagram switch On the FPGA manages flow of datagrams between the simulator and the processing units. Data processing units On the FPGA each unit processes datagrams.

5. Simulator Switch Processing unit FPGA PC

6. Each unit contains Nios II processor and C2H generated H/W accelerators. Sequence search C2H generated accelerator Histogram builder C2H generated accelerator Nios II embedded processor Avalon switch fabric Avalon switch fabric

7. for {level} := 1 up to {maximum level} do 1. Build histogram of differences (SDIF) of level:= {level}. 2. Add SDIF to cumulative histogram (CDIF). 3. Find lowest periodicity column of CDIF above threshold. 4. if {column found} = TRUE then 4.1. Detect all pulse sequences of the periodicity. 4.2. Mark pulses as associated. end if 5. Check whether to break the loop. end for

8. abcabcabcabcabc

9. abcabcabcabcabc c a b c a b

10. c a b Threshold function

11. abcabcabcabcabc a+bc+ab+c cab c+a a+b cab b+cc+a a+b

12. Threshold function cab b+cc+a a+b

13. abcabcabcabcabc c+ab+c a+b+c ca b b+cc+a a+b a+b+c ca bb+c c+a a+b

14. Threshold function a+b+c cabb+c c+a a+b Threshold satisfied by periodicity (a+b+c)

16. Input datagram format TOA 1 ID Control BitsLen TOA 2... TOA N 64 bits

17. Output datagram format Control fields set Length ID Total pulses associated Total sequences detected Association of pulse 1 Association of pulse 2 … Association of pulse N Total pulses associated with sequence 1 PRI of sequence 1 Jitter of sequence 1 Confidence level 1 of sequence 1 Confidence level 3 of sequence 1 PRI of sequence 2 … 2 2 4 4 4 2 4 2 1 1 … 1 4 4 4 … Field nameSize (bytes)

18. Implementation for Nios II Testing and profiling In Visual Studio (VS) floating point calculations were replaced by fixed point C code of the algorithm was ported from VS to Nios IDE Algorithm was profiled on Nios II

19. SoPC system generation H/w design was generated in Altera SoPC Builder environment

20. Different SoPC system configurations were compared SoPC system was optimized ◦ multiple clock domains were provided for ◦ interconnect was minimized ◦ different processor types were compared SoPC system generation

21. C2H Acceleration C2H h/w accelerators were generated for two blocks of the algorithm: ◦ Sequence search function (FindSeqs) ◦ Histogram builder function (BuildHist)

22. C2H accelerators Performance optimization Sequence search (FindSeqs) function acceleration ◦ Accelerator results unsatisfactory ◦ Consumes great amount of FPGA logic ◦ Low acceleration gain (X4 at most) ◦ Discarded after much efforts wasted in optimization

23. C2H accelerators Performance optimization Sequence search (BuildHist) function acceleration ◦ Good acceleration results ◦ X50 acceleration gain ◦ Moderate FPGA logic consumption

24. Design performance FPGA resources 6% logic consumption 5% memory consumption

25. Design performance Timing 1 up to 7 ms processing time 3 Nios systems significantly outperform Pentium 4 processor