1. CSE431 L01 Introduction.1Irwin, PSU, 2005 CSE 431 Computer Architecture Fall 2005 Lecture 01: Introduction Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~mji www.cse.psu.edu/~cg431 [Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005, UCB]

2. CSE431 L01 Introduction.2Irwin, PSU, 2005 Course Administration  Instructor:Mary Jane Irwinmji@cse.psu.edu 348C IST Building Office Hrs: T 11:30-1:00 & W 12:30-2:00mji@cse.psu.edu  TA:Reetuparna Das rdas@cse.psu.edu 111A IST Office Hrs: posted on the course web pagerdas@cse.psu.edu  Labs: Accounts on machines in 218 and 222 IST  URL: www.cse.psu.edu/~cg431  Text: Required: Computer Org and Design, 3 rd Edition, Patterson and Hennessy ©2005 Optional: Superscalar Microprocessor Design Johnson, ©1991  Slides:pdf on the course web page after lecture

3. CSE431 L01 Introduction.3Irwin, PSU, 2005 Grading Information  Grade determinates l Midterm Exam~30% -Tuesday, October 18 th, 20:15 to 22:15, Location: 113 IST l Final Exam~30% -???, December ?? th, ??:?? to ??:??, Location TBD l Homeworks (5)~30% -Due at the beginning of class (or, if its code to be submitted electronically, by 17:00 on the due date). No late assignments will be accepted. l Class participation & pop quizzes~10%  Let me know about midterm exam conflicts ASAP  Grades will be posted on the course homepage l Must submit email request for change of grade after discussions with the TA (Homeworks/Quizzes) or instructor (Exams) l December 9 th deadline for filing grade corrections; no requests for grade changes will be accepted after this date

4. CSE431 L01 Introduction.4Irwin, PSU, 2005 Course Content  Content l Principles of computer architecture: CPU datapath and control unit design (single-issue pipelined, superscalar, VLIW), memory hierarchies and design, I/O organization and design, advanced processor design (multiprocessors and SMT)  Course goals l To learn the organizational paradigms that determine the capabilities and performance of computer systems. To understand the interactions between the computer’s architecture and its software so that future software designers (compiler writers, operating system designers, database programmers, …) can achieve the best cost-performance trade-offs and so that future architects understand the effects of their design choices on software applications.  Course prerequisites l CSE 331. Computer Organization and Design

5. CSE431 L01 Introduction.5Irwin, PSU, 2005 What You Should Know - CSE271 and CSE331  Basic logic design & machine organization l logical minimization, FSMs, component design l processor, memory, I/O  Create, assemble, run, debug programs in an assembly language l MIPS preferred  Create, simulate, and debug hardware structures in a hardware description language l VHDL or verilog  Create, compile, and run C (C++, Java) programs  Create, organize, and edit files and run programs on Unix/Linux

6. CSE431 L01 Introduction.6Irwin, PSU, 2005 Course Structure  Design focused class l Various homework assignments throughout the semester l Simulation of architecture alternatives using SimpleScalar  Lectures: l 2 weeks review of the MIPS ISA and basic architecture l 2 weeks pipelined datapath design issues l 3 weeks superscalar/VLSI datapath design issues l 2 week memory hierarchies and memory design issues l 2 weeks I/O design issues l 2 weeks multiprocessor design issues l 1 week exams

7. CSE431 L01 Introduction.7Irwin, PSU, 2005 How Do the Pieces Fit Together? I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware  Coordination of many levels of abstraction  Under a rapidly changing set of forces  Design, measurement, and evaluation Memory system Datapath & Control

8. CSE431 L01 Introduction.8Irwin, PSU, 2005 How Do the Pieces Fit Together? I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware  Coordination of many levels of abstraction  Under a rapidly changing set of forces  Design, measurement, and evaluation Datapath & Control Memory system CSE 447 & 477 CSE 271 & 471 & 478 CSE 331 & 431 & 472 CSE 421 CSE 411

9. CSE431 L01 Introduction.9Irwin, PSU, 2005 Where is the Market? Millions of Computers

10. CSE431 L01 Introduction.10Irwin, PSU, 2005 By the architecture of a system, I mean the complete and detailed specification of the user interface. … As Blaauw has said, “Where architecture tells what happens, implementation tells how it is made to happen.” The Mythical Man-Month, Brooks, pg 45

11. CSE431 L01 Introduction.11Irwin, PSU, 2005 Instruction Set Architecture (ISA)  ISA: An abstract interface between the hardware and the lowest level software of a machine that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory access, I/O, and so on. “... the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls, the logic design, and the physical implementation.” – Amdahl, Blaauw, and Brooks, 1964 l Enables implementations of varying cost and performance to run identical software  ABI (application binary interface): The user portion of the instruction set plus the operating system interfaces used by application programmers. Defines a standard for binary portability across computers.

12. CSE431 L01 Introduction.12Irwin, PSU, 2005 ISA Type Sales PowerPoint “comic” bar chart with approximate values (see text for correct values) Millions of Processor

13. CSE431 L01 Introduction.13Irwin, PSU, 2005 Moore’s Law  In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time).  Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. l 2300 transistors, 1 MHz clock (Intel 4004) - 1971 l 16 Million transistors (Ultra Sparc III) l 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 l 55 Million transistors, 3 GHz, 130nm technology, 250mm 2 die (Intel Pentium 4) - 2004 l 140 Million transistor (HP PA-8500)

14. CSE431 L01 Introduction.14Irwin, PSU, 2005 Processor Performance Increase SUN-4/260MIPS M/120 MIPS M2000 IBM RS6000 HP 9000/750 DEC AXP/500 IBM POWER 100 DEC Alpha 4/266 DEC Alpha 5/500 DEC Alpha 21264/600 DEC Alpha 5/300 DEC Alpha 21264A/667 Intel Xeon/2000 Intel Pentium 4/3000

15. CSE431 L01 Introduction.15Irwin, PSU, 2005 DRAM Capacity Growth 16K 64K 256K 1M 4M 16M 64M 128M 256M 512M

16. CSE431 L01 Introduction.16Irwin, PSU, 2005 Impacts of Advancing Technology  Processor l logic capacity:increases about 30% per year l performance:2x every 1.5 years  Memory l DRAM capacity:4x every 3 years, now 2x every 2 years l memory speed:1.5x every 10 years l cost per bit:decreases about 25% per year  Disk l capacity:increases about 60% per year

17. CSE431 L01 Introduction.17Irwin, PSU, 2005 Impacts of Advancing Technology  Processor l logic capacity:increases about 30% per year l performance:2x every 1.5 years  Memory l DRAM capacity:4x every 3 years, now 2x every 2 years l memory speed:1.5x every 10 years l cost per bit:decreases about 25% per year  Disk l capacity:increases about 60% per year ClockCycle = 1/ClockRate 500 MHz ClockRate = 2 nsec ClockCycle 1 GHz ClockRate = 1 nsec ClockCycle 4 GHz ClockRate = 250 psec ClockCycle

18. CSE431 L01 Introduction.18Irwin, PSU, 2005 Example Machine Organization  Workstation design target l 25% of cost on processor l 25% of cost on memory (minimum memory size) l Rest on I/O devices, power supplies, box CPU Computer Control Datapath MemoryDevices Input Output

19. CSE431 L01 Introduction.19Irwin, PSU, 2005 PC Motherboard Closeup

20. CSE431 L01 Introduction.20Irwin, PSU, 2005 Inside the Pentium 4 Processor Chip

21. CSE431 L01 Introduction.21Irwin, PSU, 2005 Example Machine Organization  TI SuperSPARC tm TMS390Z50 in Sun SPARCstation20 Floating-point Unit Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface SuperSPARC L2 $ CC MBus Module MBus L64852 MBus control M-S Adapter SBus DRAM Controller SBus DMA SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy SBus Cards

22. CSE431 L01 Introduction.22Irwin, PSU, 2005 MIPS R3000 Instruction Set Architecture  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special R0 - R31 PC HI LO OP rs rt rdsafunct rs rt immediate jump target 3 Instruction Formats: all 32 bits wide Registers Q: How many already familiar with MIPS ISA?

23. CSE431 L01 Introduction.23Irwin, PSU, 2005 Next Lecture and Reminders  Next lecture l MIPS ISA Review -Reading assignment – PH, Chapter 2  Reminders l HW1 out next lecture, due September 13 th l Evening midterm exam scheduled -Tuesday, October 18 th, 20:15 to 22:15, Location 113 IST -Please let me know ASAP (via email) if you have a conflict