1. UPDATE ON CLICPIX2 DESIGN Pierpaolo Valerio Edinei Santin 26.03.2015 1

2. GENERAL PLANNING AND DIGITAL PART 2

3. A short summary on CLICpix2 CLICpix2 is a revised and improved version of the CLICpix prototype currently being designed Main improvements: ◦ Larger pixel matrix ( 64x64  128x128 pixels) ◦ Longer counters (8 bits ToA + 5 bits ToT) ◦ 13bits ToA/counting with no ToT mode of operation ◦ Improve shielding of sensitive analog nodes (more on this in next) ◦ Improve the communication logic ◦ Include a bandgap block 3

4. Work planning Different tasks were identified and split between the design team The schedule is feasible, but we want to prioritize having a well verified design before submission There are submissions through IMEC every two weeks. Booking a run requires only a two-week notice. 4 MarchAprilMayJune W2W3W4W1W2W3W4W1W2W3W4W1W2W3W4 Comparator architecture comparison and evaluation (Throughout) simulation of the digital pixel with a new testbench Study of “large matrix” effects (power drops, biasing lines, signal delays…) Study of isolation possibilities (triple well?) Update of end of column, periphery logic to accommodate larger matrix Layout of the analog pixel Extracted simulations of analog + digital to evaluate specs fulfilment Implement 8to10 encoding logic Writing a better digital testbench + digital simulations Band-gap IP simulation and implementation Final chip assembly and verification (+ safety margins)

5. Updated pixel logic The logic has been updated and resynthesized It now includes longer counters, a new ToA-only mode and fixed zero-compressed readout It is slightly bigger than before: 200 by 25.2 µm for a group of 16 pixels (it was 200 by 22.6 µm before) The additional area takes the place of the shared blocks on the analog side 5

6. Simulation of the new counters The new counters are still LFSR (pseudo-random) counters, but they’re not full-length anymore, to reduce complexity. The loss of dynamic range is negligible anyway: ◦ The 5-bit ToT counter has 31 possible codes ◦ The 8-bit ToA counter has 255 possible codes ◦ The combined 13-bit ToA counter has 8191 codes The 13-bit counter is obtained by connecting the ToA and ToT counters together and by generating the next code by checking a new set of bits. This solution was found to be simpler than using the overflow bit of one counter as the clock for the other Overflow control is applied to all the counters 6

7. Simulation of the new counters 7 …

8. Tests with random pulses 8

9. Some notes on the simulations The pixel logic was simulated as a complete block: signals sent from the testbench were only physical lines from the periphery (or the analog pixels) Multiple pixel clusters in a column were simulated at once, to make sure that data can be correctly shifted in or out of the matrix Simulations were performed taking into account processing corners variations 9

10. Next steps for the digital design The rest of the logic, outside of the pixels, needs to be updated to accommodate for the bigger matrix The whole system needs to be accurately simulated to calculate “macroscopic” effects, such as the delay of signals going from the periphery to the top of the columns. The periphery will be updated to use an 8- to-10 bit encoder for the chip data output 10

11. ANALOG PART 11

12. Analog front-end (per pixel) 12 [Valerio Thesis, p. 64] to digital logic Charge-sensitive amplifier Comparator Calibration DAC

13. Analog front-end layout (CLICpix1) 13 [Valerio Thesis, p. 81] Area: 25x14 µm 2 (~ 60% of px area) DAC Calibration Comparator Amplifier Charge-Sentitive

14. Comparator specs 14 ParameterValue Calibrated input-referred offset *< 1 mVrms Propagation delay **<< 10 ns Power dissipation< 5 µW Area< 70 µm 2 * Including the contribution of the CSA offset. ** For an input signal ≥ 20 mV.

15. Previous comparator 15

16. Improved comparator 16

17. Uncalibrated vs calibrated comparator 17 Same calibration scheme can be applied to both (old & new) comparator topologies

18. Next steps for the analog part Finish comparator sizing Compare comparators performance Analyze the charge-sensitive amplifier, and maybe improve its sizing Layout of the analog front-end ◦ Substrate noise and crosstalk isolation ◦ Power and biasing signals distribution Post-layout simulations Integration with the digital part and final verification 18

19. Thank you! 19