1. Lecture No. 29
Sequential Logic

2. Recap Decade Counter timing diagram Mod-n Synchronous Counter
IC 74HC163 Mod-16 Counter
IC 74HC160 Mod-10 Counter

3. Digital Logic & Design
Dr. Waseem Ikram
Lecture 29

4. Up-Down Synchronous Counter

5. Timing diagram of an Up-Down Synchronous Counter

6. 74HC190 4-bit Synchronous Up/Down Counter

7. Decoder circuit decoding counter outputs 4, 8 and 12

8. Decoded Outputs of Synchronous Counter

9. The Decoder circuit connected to remove glitches

11. 3-bit Synchronous Down-counter

12. Up-Down Synchronous Counter

13. Timing diagram of an Up-Down Synchronous Counter

29. Recap Cascading Counters Counters with truncated sequences
IC counters with truncated seq.
IC 74x161 counter with Asyn. Clear
Cascading counters with truncated sequence
Up-Down Counter

30. Up/Down Counter Up/Down Counter IC 74HC190 Up/Down Counter (fig 3)
3-bit down synchronous down counter (fig 1)
Up-down counter (fig 2)
IC 74HC190 Up/Down Counter (fig 3)

31. Decoding Counter Counter Decoding (fig 4, 5)
IC Counter Decoding (fig 6, 7)

32. Counter Applications Digital Counter (fig 8)
Divide by 60 counter (fig 9)
Hours Counter circuit (fig 10)
Frequency Counter (fig 11)
Sampling intervals (fig 12)
Detailed Circuit diagram (fig 13 )

33. Design of Sync. Counters
Sequential circuits (fig 2)
State diagram (fig 3)
Next-State table (tab 1)
Flip-flop transition table (tab 2)
Karnaugh maps (tab 3, 4)
Logical expressions for flip-flop inputs
Sequential circuit Implementation (fig 4)

34. Implementation of 3-bit Up/down Counter
State diagram (fig 5)
Next-State table (tab 5)
Flip-flop transition table (tab 6)
Karnaugh maps (tab 7, 8)
Logical expressions for flip-flop inputs
Sequential circuit Implementation (fig 6)