1. R&D status of the very front end ASIC Tilecal week (7 October 2011) François Vazeille Jacques Lecoq, Nicolas Pillet, Laurent Royer and Irakli Minashvili  Status by June 2011  New results  Conclusion and next steps  Status by June 2011  New results  Conclusion and next steps 1

2. 2

3. Status by June 2011  The first chips in IBM 130 nm technology were made (CERN order) then tested at Clermont-Ferrand - First one: only a current conveyor. - Second one: current conveyor + shaping stage. With 3 different gains (1, 8, 64) for the two chips. 1.7 cm 0.8 cm Chip 1 Chip 2 3

4.  Main results - They work. - A good correlation between the 3 gains. - Dynamics fully effective. - Good agreement with simulations. BUT: - Large offset for the 3 gains: solved (due to a lay out problem). - Oscillation problems  length of wire bonding to the package: cured by adding an external R-C. - Linearity not well tested because the test bench generator is not enough precise. - Pulse width not optimized with respect to Tilecal needs, because of the cure of the oscillation problems (pulse tail).  New studies of integrator - Needs of a very high gain and of a very small offset. - A compromise choice could associate 2.7 V “analog” transistors and 1.6 V transistors (low power). 4

5.  Next steps foreseen by June □ Chip 2: - Tests behind a PMT at Clermont-Ferrand using Laser pulses (Scheduled in July)  More realistic situation.  A first approach of the absolute scale/Chip design. -Tests with cosmics at CERN inside a Tilecal module (Scheduled in September)  The most realistic detector using real particles.  A better approach of the absolute scale/Chip design.  A good learning exercise around a Tilecal module. □ Integrator - Simulations of the new design. - Goal:  To reach the performances of the Chicago amplifier (discrete solution): Gain of 50 000 and max offset < 1 mV. 5

6. New results Chips 1 and 2  Identity names Chip1  FATALIC 1 Chip 2  FATALIC 2  Laser pulses at Clermont-Ferrand (July) Front end for Atlas Tile cAL Integrated Circuit (IC for every Clermont chips) - The first time behind a PMT and with light. - Large uncertainty on the Laser amplitude (10 to 20%). But first check of the dynamical range (in equivalent charge) for the 3 gains. 6

7.  Cosmics at CERN (September): building 175. 7

8. Long cable D cell LED signal: Oscillation due to the 4 m long cable, with a circuitry not suited to it. Super-drawer LBA65 #27 PMT # 1 Hv out = 678.5 V (setting: 678.0 V) calibrated with Cesium. 8

9. Muon signals: first particle events seen by FATALIC2 ~ One event every 2 minutes. Choice of the high gain (64)  saturation of many events above 500 mV It was not the best choice ! 9

10. - D cell   1 GeV muons (Claudio information)  50 pC - Gain 64: 625 µA max or 12 pC  Saturation of many pulses. Nevertheless, these results do confirm the first approach of the requested scale: - Gain 64: 625 µA or  12 pC max. - Gain 8: 6.25 mA or  120 pC max. - Gain 1: 62.5 mA or  1200 pC max. 10

11.  New Integrator simulations of amplifier Bode diagram: Gain > 50 000 Output offset (gain = 1 000): 86 µV converted to input (Monte carlo with 500 events)  Results fitting the goals (Chicago reference). 11

12. Conclusion and next steps  The chips have “seen” light: laser (Clermont-Ferrand) and cosmic particles (CERN).  These tests put the chips in realistic environments, besides, it was a good learning for everybody.  The absolute choices of the gains and ranges are not far away the physical needs.  New steps are scheduled. 12

13.  New foundry order on November 7 th  FATALIC 3 Circuit corrected + Integrator amplifier. + inside: capacitor and resistor used to reduce parasitic self effects due to cable length.  Parallel studies - Improvement of the test bench (In particular by buying an “expensive” generator for precise linearity tests). - Pulse width, peaking time. - ADC studies. - CIS part. - Analog output for trigger. - Environment (3in1 card, LV regulators, MB-2, data format, DCS, connections…) with contributions of both micro-electronics and electronics people. 13 Expensive:  10000 $

14. FE-ASIC alternative Feasibility testsDone Design ASIC FATALIC 1 & 2 in IBM 130 nmDone Test FATALIC1 & 2 @ C-FDone Test FATALIC2 in Bld 175Q3-11 Design FATALIC3Q4-11 Test FATALIC3 @ C-FQ2-12 3in1 prototype designQ4-11 3in1 prototype tests at C-F Q1-12 Prototype design of MB-2 (similarto3-in-1 DB)Q4-11 MB-2 prototype tests at C-FQ2-12 System tests in Bld 175Q3/Q4-12 Design of FATALIC4 (ADC)Q2-12 FATALIC4 tests at C-F Q4-12 Radiation tests Q1/Q2-13 Final designs for production Q3-13 Tests in test beam Q3-14 Comments: Depending from the true upgrade schedule, the above “final” design could be reviewed a new time if more time is available. … towards a very aggressive planning !!! Question: is it judicious to speed up the studies while Phase 2 is starting … many years later ? 14