1. EE141 Timing Issues 1 Chapter 10 Timing Issues Rev.1.0 05/11/2003 Rev. 1.1 05/28/2003 Rev. 1.2 06/05/2003

2. EE141 Timing Issues 2 Synchronous Pipelined Datapath In t pd,reg t pd1 D R1 Q CLK Logic Block #1 t pd2 D R2 Q Logic Block #2 D R3 Q Out Data Register Output Register

3. EE141 Timing Issues 3 Self-Timed Logic (Asynchronous Datapath) Check Textbook (Sec. 10.4) for details!

4. EE141 Timing Issues 4 Latch Parameters D Clk Q D Q t c-q t hold PW m t su t d-q Delays can be different for rising and falling data transitions T t c-q Positive Latch

5. EE141 Timing Issues 5 Register Parameters D Clk Q D Q t c-q t hold T t su Positive Edge-Triggered Register

6. EE141 Timing Issues 6 Sources of Clock Uncertainties 2 : Device Variations 5 : Temperature

7. EE141 Timing Issues 7 Clock Nonidealities  Clock skew  Spatial variation in temporally equivalent clock edges: deterministic + random,  Clock jitter  Temporal variations in consecutive edges of the clock signal: modulation + random noise  Cycle-to-cycle (short-term) t Jitter  Long-term t Jitter  Variation of the pulse width  Important for level-sensitive clocking

8. EE141 Timing Issues 8 Clock Skew and Jitter  Both skew and jitter affect the effective cycle time Clk t SK t JS

9. EE141 Timing Issues 9 Clock Skew (Distribution) # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal –  /2 Latest occurrence of Clk edge Nominal +  /2 

10. EE141 Timing Issues 10 Positive and Negative Skew

11. EE141 Timing Issues 11 Positive Skew Launching edge arrives before the receiving edge

12. EE141 Timing Issues 12 Negative Skew Receiving edge arrives before the launching edge

13. EE141 Timing Issues 13 Datapath Structure with Feedback

14. EE141 Timing Issues 14 Positive Skew Launching edge arrives before the receiving edge

15. EE141 Timing Issues 15 Timing Constraints Minimum cycle time (  fastest clock rate): T +  >= t c-q + t logic + t su Eq. (10.3) Has the potential to improve the performance (  >0)

16. EE141 Timing Issues 16 Timing Constraints Hold time constraint: t hold +  < t (c-q, cd) + t (logic, cd)  Race between data and clock   should be kept small

17. EE141 Timing Issues 17 Impact of Jitter CLK In Combinational Logic t c-q, t c-q, cd t logic t logic, cd t su, t hold REGS t jitter CLK -t-t jitter T CLK t jitter     T – 2 t jitter >= t c-q + t logic + t su Eq. (10.5)

18. EE141 Timing Issues 18 Combined Impact of Skew and Jitter T +  – 2 t jitter >= t c-q + t logic + t su Eq. (10.6) t hold +  < t (c-q, cd) + t (logic, cd) – 2 t jitter Eq. (10.7)

19. EE141 Timing Issues 19 Latch-Based Design L1 Latch Logic L2 Latch  L1 latch is transparent when  = 0 L2 latch is transparent when  = 1

20. EE141 Timing Issues 20 Latch-based Design

21. EE141 Timing Issues 21 Edge-triggered Pipeline Design

22. EE141 Timing Issues 22 Slack-borrowing (Sec. 10.3.4)

23. EE141 Timing Issues 23 Clock Distribution Clock is distributed in a tree-like fashion H-tree

24. EE141 Timing Issues 24 More realistic H-tree [Restle98]

25. EE141 Timing Issues 25 The Grid System No rc-matching Large power

26. EE141 Timing Issues 26 Example: DEC Alpha 21164

27. EE141 Timing Issues 27 21164 Clocking  2 phase single wire clock, distributed globally  2 distributed driver channels  Reduced RC delay/skew  Improved thermal distribution  3.75nF clock load  58 cm final driver width  Local inverters for latching  Conditional clocks in caches to reduce power  More complex race checking  Device variation t rise = 0.35ns t skew = 150ps t cycle = 3.3ns Clock waveform Location of clock driver on die pre-driver final drivers

28. EE141 Timing Issues 28

29. EE141 Timing Issues 29 Clock Skew in Alpha Processor

30. EE141 Timing Issues 30  2 Phase, with multiple conditional buffered clocks  2.8 nF clock load  40 cm final driver width  Local clocks can be gated “off” to save power  Reduced load/skew  Reduced thermal issues  Multiple clocks complicate race checking t rise = 0.35nst skew = 50ps t cycle = 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform

31. EE141 Timing Issues 31 21264 Clocking

32. EE141 Timing Issues 32 EV6 Clock Results GCLK Skew (at Vdd/2 Crossings) ps 5 10 15 20 25 30 35 40 45 50 ps 300 305 310 315 320 325 330 335 340 345 GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%)

33. EE141 Timing Issues 33 EV7 Clock Hierarchy + widely dispersed drivers + DLLs compensate static and low- frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks Active Skew Management and Multiple Clock Domains

34. EE141 Timing Issues 34 Summary  Clocking schemes are very important in synchronous circuit designs  dominated in speed performance and power consumption.  Clock jitter and skews should be considered in early design phase.  Phase-locked loop (PLL) and Delay-locked loop (DLL) circuits are used to reduce the clock jitter and skews.  Good clock distribution CAD tools are useful in analyzing the clock performance in modern chips.