1. Mai 31th 2011 Christophe Beigbeder PID meeting1 ETD meeting Test setup : Activities in Bari, Univ of Maryland and at Orsay Test setup : Activities in Bari, Univ of Maryland and at Orsay Development of the 16 channel waveform digitizer Development of the 16 channel waveform digitizer : design status SCATS : design status Implementation Implementation Conclusion Conclusion

2. Mai 31th 2011 Christophe Beigbeder PID meeting2 The MaPMT scanning setup is almost ready The MaPMT scanning setup is almost ready The layout is the one shown in the past meetings The layout is the one shown in the past meetings The DAQ system is ready The DAQ system is ready The code is written in LabView and CVI The code is written in LabView and CVI The tools could be shared among the groups to have a common framework The tools could be shared among the groups to have a common framework We are performing preliminary measurements on the set-up We are performing preliminary measurements on the set-up CAEN 64ch ADC and 64ch TDC calibration (and linearity studies) CAEN 64ch ADC and 64ch TDC calibration (and linearity studies) Cross talk from the cables to the read-out boards Cross talk from the cables to the read-out boards The dedicated electronic front-end is in production The dedicated electronic front-end is in production Our electronics is tailored to be used with our ADC (CAEN VN1488) and TDC (CAEN VN1465) Our electronics is tailored to be used with our ADC (CAEN VN1488) and TDC (CAEN VN1465) Differential Output for Charge measurements Differential Output for Charge measurements Differential ECL Output for timing measurements Differential ECL Output for timing measurements Tests with different electronics are planned Tests with different electronics are planned Setup @ Bari

3. Mai 31th 2011 Christophe Beigbeder PID meeting3 They have developed a system for measuring and scanning phototubes for the FDIRC They have developed a system for measuring and scanning phototubes for the FDIRC Based primarily on being able to measure Hamamatsu H8500, but should be flexible enough to look at other possibilities as well Based primarily on being able to measure Hamamatsu H8500, but should be flexible enough to look at other possibilities as well Readout is done using a new waveform digitizer VME card from CAEN Readout is done using a new waveform digitizer VME card from CAEN Just received second card less than two weeks ago, so all results are very preliminary; qualitative not really quantitative Just received second card less than two weeks ago, so all results are very preliminary; qualitative not really quantitative Caen module 5 Gs /32 channels Scale: 5 ns / div in X 1kV HV Soft CFD algorithm Distribution with sigma around 210 ps. Setup @ Univ of Maryland

4. Mai 31th 2011 Christophe Beigbeder PID meeting4 Mezzanine : - CFD/ CFD like + Amp for charge measurement. - PIF chip in next version -> equips both PM test setup @ Orsay,CRT and Bari Start to develop a simple setup with to test the electronics Mother board : ADC + Scats + FPGA - Associate time & charge - Data packing. - Bus interface : USB, GVbus -> equips both PM test setup @ Orsay and CRT Setup @ Orsay

5. Mai 31th 2011 Christophe Beigbeder PID meeting5 Under design: a 16-channel WaveCatcher Based on the very encouraging results of the 16-channel crate, we started the design of a 16-channel WaveCatcher board This board will be compatible with both SAM (256 cells/ch) and SAMLONG (1024 cells/ch) –The board can be synchronized externally => possibility to scale the system up to 320 channels in a crate The first prototype will be available in September 2011 SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC 4 Analog Input Trigger In/out SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC FPGA 4 Analog Input Trigger In/out FPGA  VME Format  USB 480 Mbits/s  Optical fiber output

6. Mai 31th 2011 Christophe Beigbeder PID meeting6 Board features (not exhaustive)  Possibility to add a individual DC offset on each signal  Possibility to chain channels by groups of 2  2 individual trigger thresholds on each channel  External and internal trigger + numerous modes of triggering on coïncidence (11 possibilities including two pulses on the same channel => useful for afterpulse studies  Embedded digital CFD for time measurement  Embedded signal amplitude extraction  Embedded charge mode (integration starts on threshold or at a fixed location) => high rates (~ 3.5 kEvents/s)  2 extra memory channels for digital signals  One pulse generator on each input  External clock input for multi-board applications  Embedded USB and Ethernet interfaces

7. Mai 31th 2011 Christophe Beigbeder PID meeting7 Status of PCB design (as of last Friday)

8. Mai 31th 2011 Christophe Beigbeder PID meeting8 SCATS : functional synopsis

9. Mai 31th 2011 Christophe Beigbeder PID meeting9 Layout synopsis Layout done. Simulation post layout done for the Ram. To be done for the 2 channel block. Layout on going Simulation post layout will follow Layout on going Post synthesis problems to be fixed Simulation post layout will follow

10. Mai 31th 2011 Christophe Beigbeder PID meeting10 The layout of Scats ( digital part ) gives precious information for post layout simulations and for detecting timing problems and underwent a complete fault coverage. We need to simulate RAM with specs extracted from the layout simulation Write pulse min width: 500 ps Read pulse min width : 1ns Rd to output : ~ 3 ns Set up and Hold time : ~ 200 ps These parameters are integrated in Verilog ram simulation model. Post layout simulation possible with a very performant simulation test bench SCATS : Digital part Scats_digital layout 948µm x 933 µm

11. Mai 31th 2011 Christophe Beigbeder PID meeting11 En Fifo1 En Fifo2 16 W0W1 W7 W0W1 W7 32 B 120µm 1000µm AMS CMOS 0.35µm technology Elementary memory cell

12. Mai 31th 2011 Christophe Beigbeder PID meeting12 Asic_fifo_control block of Scats : 591µm x 50µm Pcsm block of Scats :131µm x 50µm Each of the following blocks must not exceed a height of 50µm to match topological design constraints

13. Mai 31th 2011 Christophe Beigbeder PID meeting13 3300µm 440µm 32-bit wide * 8-word long FIFO Fine Time measurement: DLL Two channels block layout

14. Mai 31th 2011 Christophe Beigbeder PID meeting14 Electronics is split in two parts : - one directly mounted on the PM base receiving the PM signal and processing it with TDC/ADC - the other one concentrates and pack all the channels to send data to the DAQ Electronics on the detector : Mechanical constraints ->FBLOCK design Thermal constraints -> 200 w per crate Power distribution issues. ->Could use rad hard power supply like LHCb Cables and links Only one link per sector

15. Mai 31th 2011 Christophe Beigbeder PID meeting15 FBLOCK PCB FE boards plugged into “crate slots” PCB FE boards plugged into “crate slots” PCBs and backplane(s) partitioned in columns could be removed “completely” PCBs and backplane(s) partitioned in columns could be removed “completely”

16. Mai 31th 2011 Christophe Beigbeder PID meeting16Conclusion Set up for PM tests and electronics test are well on tracks We start the design of the mezzanine board Version with commercial components (CFD like). Version with PIF ( not before next year ) Version associated with Caen ADC and TDC module Schematics of the 16 channels channel waveform digitizer is almost finished PCB half done. Choice on the architecture has to be maid link to mechanical issues SCATS : layout of the 16 channel, simulation post synthesis and post layout are on going Submission still foreseen for July