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Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue
S. m. Y. Sherazi & J. Ryckaert with contributions from all insite team ISPD 2016 Invited Talk
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Design-Technology co-optimization as process technology pathfinder
EUV DSA SAxP DTCO -3 -2 -1 YOP Technology options screening Development Yield Ramp Production DTCO mission Down-select scaling scenarios Define process assumptions sets and ground rules Identify and verify key technology enablers for design
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Scaling roadmap to N7 and beyond
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Scaling roadmap to N7 and Beyond
Metal 2 pitch around 32nm CPP pitch around 42nm
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Scaling roadmap to N7 and beyond
193i will be based on SAQP 1D metals only EUV insertion in mix-match (vias/cuts) Designers need to help find the optimal patterning scheme Metal 2 pitch around 32nm CPP pitch around 42nm
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Many issues need to be resolved at design level
Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? E.g. what is the optimal track height How 1D interconnect impact the MOL scheme?
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Many issues need to be resolved at design level
Designers can define scaling paths that allow optimal area scaling 5 DTCO cases will be discussed: Optimal MOL patterning scheme Fin depopulation Optimal 1D routing scheme Design rules simplification New device architecture Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? Will 1D interconnect impact the MOL?
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Many issues need to be resolved at design level
Designers can define scaling paths that allow optimal area scaling 5 DTCO cases will be discussed: Optimal MOL patterning scheme Fin depopulation Optimal 1D routing scheme Design rules simplification New device architecture Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? Will 1D interconnect impact the MOL?
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Partially self-aligned MOL
Gate Via0 Gate Cap Spacer Active contact ILD0 Gate contact N10 used a partially self-aligned MOL All active contacts where patterned individually
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Partially self-aligned MOL requires 5 blocks in the SRAM
Using this scheme at a 42nm CPP and assuming an SADP + block patterning for active contacts Leads to 5 block masks to print the active contacts
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Fully self-aligned MOL
Gate Via0 Gate Cap Spacer Active contact ILD0 Gate contact Now consecutive active contacts can be printed using one constructs thanks to the fully self-aligned scheme
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Fully self-aligned MOL reduces the mask count
In this scheme 2 stitched direct LE prints can print the active contacts This solution enables a: 2 color decomposition Larger process window
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Many issues need to be resolved at design level
Designers can define scaling paths that allow optimal area scaling 4 DTCO cases will be discussed: Optimal MOL patterning scheme Fin depopulation Optimal 1D routing scheme Design rules simplification New device architecture Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? Will 1D interconnect impact the MOL?
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Fin depopulation allows area reduction
9T = 4+4 active fins 7.5T = 3+3 active fins Fin depopulation relies on device performance improvement to reduce the standard cell template hence achieving area scaling
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Fin depopulation requires fin height increase
Increasing fin height increases the effective width of the FET But improvement will depend heavily on parasitics!
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Balancing currents means balancing resistances
Channel resistance reduction needs to balance source-drain parasitic increase
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Problem is parasitic resistance increases largely at N7
Increasing resistance is due to the low contact area at N7 At 7e-9 Ohm.cm2 the 3 fin device never matches the 4fin device
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Reducing contact resistivity allows fin depopulation
Allowing a 7.5T standard cell to perform equally to a 9T standard cell, all pitches remaining constant.
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Many issues need to be resolved at design level
Designers can define scaling paths that allow optimal area scaling 4 DTCO cases will be discussed: Optimal MOL patterning scheme Fin depopulation Optimal 1D routing scheme Design rules simplification New device architecture Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? Will 1D interconnect impact the MOL?
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What you see is not what you get
Reality... Narrowing Pull back Rounding Proximity Drawn... Expectation... Imec 10nm layout with LELELE M1 (64nm CPP – 48nm MP)
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Designers layout have a long life after gds-out
Advanced patterning requires multiple patterning Decomposition may lead to very different patterns Should designers be aware of layout post-processing? Can EDA accommodate?
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transition between FEOL and routing layers
1st Mx routing (M2) runs horizontal Intermediate layers (e.g. MOL, M1) must provide: Intra-cell routing Interface between FEOL and Mx routing Gates run vertical
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M1 vertical important for port accessibility to router
Complex MOL required to shift FEOL pins to M1 grid Congested M2: all horizontal connections shifted to M2
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CPP to Mx pitch gear ratio created patterning conflicts
Cells are placed on the CPP grid Resulting in M1 constructs out of grid
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Adding a layer under vertical M1: Mint
Mint Optimal connectivity to FEOL and to routing layer Limits M2 usage inside the cell Requires introduction of extra layer (Mint):
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Mint reduces the M1 complexity
Example on a ND2D1 M2 M2 VDD VDD VDD VDD ZN A ZN B Mint power rail A B Mint shift gate connect ZN ZN VSS VSS M2 M2 Mint fly over gate for S/D Without Mint: Requires M2 to finish cells Multiple M1 constructs Poor port access With Mint Limited M2 usage Few M1 constructs Optimal port access
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M2 usage reduction with Mint Example on an XNOR2D1
9T version 7.5T version With 5 DP Mint tracks 7.5T version With 7 QP Mint tracks 0/5 tracks used 7/7 tracks used 3/5 tracks used
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Scaling Cell Height using Boosters
7.5T version With 7 QP Mint tracks 0/5 tracks used 6.5T version With 5 QP Mint tracks and Fully Self Aligned gate contact 6T version With 5 QP Mint tracks and Fully Self Aligned gate contact + Buried Power rail 1/6.5 tracks used 1/6 tracks used 6.5T = 6 T in number of poly used in the cells Height = 240nm Height = 192nm Height = 208nm
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Buried Rails and Fully Self Aligned Gate contact (FP=24)
P gate P-Well P-substrate N-well Cell boundary P-fins N-fins VDD VSS P-N boundary W buried rail Buried rail isolation Buried rail cap
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Poly Count Comparison b/w 7.5T, and 6T
378nm 384nm 20-Poly 630nm 480nm 30-Poly 6T DH Poly Count 6.5T/6T < 7.5T 61.2% 6.5T/6T = 7.5T 38.8% 6.5T/6T > 7.5T 0% 7.5T DH 6T with Buried PR + FSAG 6.5T with FSAG 7.5T
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Many issues need to be resolved at design level
Designers can define scaling paths that allow optimal area scaling 5 DTCO cases will be discussed: Optimal MOL patterning scheme Fin depopulation Optimal 1D routing scheme Design rules simplification New device architecture Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? Will 1D interconnect impact the MOL?
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Need for simplification
Explosion of design rules because ... Designers don’t know technology constraints... Technologists don’t know what designers expect Need for simplification
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What’s left on the table as latest node is being enabled templated design
Don’t ask for flexibility constrained by complex design rules Define a patterning friendly template VSS A B OUT VDD Via size T2T Via spacing Min metal area Via enclosure Focus on key DFM rules
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4 basic templates are used in 7.5-Track STD-Level
gate Internal Vdd Internal Vss S/D or gate S/D A B C D This will ensure regular patterns at each layer
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“design aware” manufacturing
Example: Litho-friendly place and route Poor Yield: Complex patterning scheme Metal density varied Better Yield: Simple patterning scheme Uniform Metal density Better Performance Lower power and higher perf. Poorer Performance Cap increase leading to power/performance drop
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“design aware” manufacturing
Example: Litho-friendly place and route Modification of cut/block process assumptions Better Yield: Patterning remains simple Little compromise on metal density Better Performance Minimize cap insertions for acceptable power/performance
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Many issues need to be resolved at design level
Designers can define scaling paths that allow optimal area scaling 4 DTCO cases will be discussed: Optimal MOL patterning scheme Fin depopulation Optimal 1D routing scheme New device architecture Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility I Z How many routing tracks do I need to intercept? How many fins per device do I need? Will 1D interconnect impact the MOL?
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Scaling roadmap to N5 Metal 2 pitch around 24nm CPP pitch around 30nm
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Vertical FETs introduction
G 3D view of an SRAM Cross-section D M1, M2 3D view of an SRAM with gate and nanowire TE Gate BE LG CGP
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Motivation Source/Drain contact challenges!!!
Unit resistance Source/Drain contact challenges!!! Lg CGP High density or small footprint device would be helpful in an increasingly high resistance interconnect world
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SRAM layouts: vertical M1 and horizontal M1
WL WL PD PG PD PG area PU PU PU PU PG PD PG PD
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conclusion Scaling cannot only rely on lithography. Self-alignement techniques become key Design technology co-optimization is necessary to enable further technology scaling Solutions need to be tuned to design benchmarks such as standard cells and SRAMs Down the road, new device architectures e.g. VFET must be considered
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Thank you !
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