1. Atlas LPNHE M. Bomben, pour le groupe R&D

2. -Development of sensor simulations models -Test of produced edgeless sensors -Reduced thickness sensors - New sensor n-in-p productions - Testbeam organization - Testbeam development (miniTLU) - Electronics - ATLAS Track trigger (AM chip) - Developments post-FE-I4 Activities in the field of sensors / electronics

3. Device simulations (Silvaco) Consolidate the general expertise acquired in these years in the field of device simulation Development of specific models Insertion of intermediate levels in the gap to reproduce the Si/SiO2 interface defects after radiation and better describe the leakage current and breakdown behavior Good agreement with measurements on our n-in-p device production https://indico.in2p3.fr/conferenceDis play.py?confId=9786

4. Edgeless sensors with DRIE (FBK/LPNHE project) Deep trench diffusion (to prevent electrical field on the damaged cut) Cut line Trench definition is critical: - aspect ratio: 20:1 - deep etching: 200-230um - trench width: 8-12um ● Goal: make the rim zone equipotential ● How: DRIE as for 3D process ● Trench doped by diffusion

6. IV and breakdown

7. Studies of current, depletion voltage, capacitances for different process parameters

8. Sensors bump-bonded at IZM

9. Setup for source scans

10. Scan with 90 Sr source 90 Sr, USBpix selfTrigger, 1M triggers

11. Tuning Threshold Noise

12. Thr = 2000e, 7 ToT @ 14000e, Vbias = -30 V Collected charge distribution

13. New this sensors productions Common ATLAS-CMS production at FBK (paid by INFN) n-in-p, 100-130um different guard-ring configurations First test of new ATLAS punch-trough biasing scheme Alpine Stave double chip sensor prototype Delivered before the end of the year New edgeless production in 2015 (INFN)

14. Pixel testbeams coordination for ATLAS (M.Bomben) New Trigger Logic Unit developed within AIDA by LPNHE It is the successor of the EUDET TLU. AIDA miniTLU is a FMC plug-in card for FPGA evaluation boards. Firmware available for low-cost SP601 and SP605. 4 scintillator inputs, 0.78 ns time reso 3 DUT interfaces High rate synchronous mode, EUDET compatible asynchronous mode Readout is done via ethernet using IPBus protocol. New software written from scratch by LPNHE to integrate the miniTLU in the EUDAQ2 data acquisition framework Developement of the new testbeam miniTLU Testbeams

15. Electronics Involvement in 65nm electronics - LPNHE is part of the AIDA EU project (providing a number of IP blocks for WP3) Support card for OmegaPix irradiation tests - Contributions to OmegaPix2 chips - FastTrack (AM chip) - RD53 (R. Beccherle convener of I/O WG)

16. Status of OmegaPix2 Bilan Tests Chip 2D (96 x 24) Bilan des tests du circuit 2D digital – Configuration correcte à 10 MHz – Ecriture correcte des cellules à 40 MHz Relecture correcte à 10 MHz Possibilité d’amélioration – Temps de stockage variable selon la technologie des cellules: de quelques ms à quelques 10 ms La Suite – Réglage du problème de relecture à 10 MHz maximum – Test d’irradiation

17. Temps de stockage Insertion d’un temps d’attente ( ordre de grandeur ms ) entre l’écriture d’un pulse et sa relecture 6,5ms9,8 ms = OK Chip 2D

18. Temps de stockage (2) Tps de stockage de ~5ms à 15ms selon le type de cellule 11 ms13 ms = OK Chip 2D

19. Tests du Chip 3D au LPNHE Reçu 2 circuits. Testé un seul pour l’instant Tests numériques OK. Résultats similaires à ceux du circuit 2D digital Temps de stockage plus faibles que pour le 2D Chip 2DChip 3D 6,5ms = OK

20. FastTrack at LPNHE AMchip05: last prototype before AMchip06, the final chip. Functional and pin compatible with AMchip06 → can be used to test all boards and FTK integration Its production has been a major step in the FTK schedule Arrived at the beginning of the Summer 2014. Under test right now. Very good results so far. LPNHE is co-responsible of the AMchip dev AMchip testing is done with an FMC mezzanine mounted on FPGA evaluation board. LPNHE has developed a base firmware + python software library based on IPBus to interact and test the AMchips from a PC with this test environment This firmware/library has been further developed by INFN Pisa, Milano and Frascati in collaboration with LPNHE for the current AMchip05 tests

21. AMchip06 design is already in an advanced stage. Final design integration, simulation and tape-out by LPNHE and INFN Milano. Tape-out December 2014 → tests march 2015 FastTrack at LPNHE Bank pattern optimization (barrel-endcap)

22. Activities in the field of mechanics Traditional contribution to the IBL mechanical design and construction (D. Laporte)

23. Mécanique : outillages Mock-ups and tooling (surface and PP1)

24. Activité X/X0 pour la determination de la quantité de matière de l’IBL

25. Results at end rings mm Angle

26. Future : Micro-channel cooling REFLECS (IN2P3 approved project) We’ll be responsible (with CERN) for micro-channel Working Package in AIDA-II proposal: Other institutions in this Working Package: DESY – Goettingen – INFN Pisa - Uni. Padova – LAL – FBK “External” institutions (not in the package): Valencia - Bonn More uniform cooling, less material in the system, less cooling fluid (strong point in industrial applications)

27. Padova / Paris Simulations DESY / Goettingen LPNHE / LAL / Pisa / MPP Device prototyping Study of base processes IZM FBK/IE F CERN/Oxford Testing facilities Device fabrication Other tasks

28. From D. Del Col (Univ. Padova) Simulations Numerical simulation of heat transfer during condensation Simulation and measurements of flow boiling in microchannels Effect of channel geometry and surface roughness on frictional pressure gradient hydraulic behaviour Effect of surface properties on flow boiling

29. Different technologies: - foams - bulk etching (DRIE) Examples at NA62/LHCb (CERN/CSEM) other prototypes with FBK Light prototype support using micro-channel technology as high efficiency system for silicon pixel detector cooling, NIMA 650, Issue 1, 2011, 213 F. Bosi, G. Balestri, M. Ceccanti, P. Mammini, M. Massa, G. Petragnani, A. Ragonesi, A. Soldani - individual micro-channels glued together FBK, IZM through Goettingen/DESY, IEF Paris Pisa Prototyping

30. Silicon wafer 4’’ Metallic layer (heater) deposited on top of the channels Inlet 1 Inlet 2 Inlet 3 Outlet 3 Outlet 2 Outlet 1 Metal pad for brazing connectors (Ti/Au or better Ti/Ni/Au) Anodic bonding with 2mm pyrex Central hole for thermal insulation Hand-brazed connectors First step: Measuring model parameters in collaboration with CERN and Padova groups (device submitted to IEF Paris)

31. In addition to LAL, which is participating with us to the AIDA-2 call, discussions with LAPP for collaborations on u-channel cooling systems (LAPP has large experience in connections and brazing techniques) Interest also by CPPM ? The critical (but interesting) points for us are: 1) Better knowledge/development of the base theory 2) for ATLAS: optimization of the channel design based on 1) and development of interconnection technologies

33. C’est tout

34. backup

35. One slide on track trigger FastTracKer : a hardware track finder for ATLAS Trigger Full silicon detector acceptance, pT > 1 GeV Tracks with ~offline quality reconstructed parameters available to level-2 processors FTK reads hits at L1 rate and reconstructs the event in ~100 μs Two step algorithm: Pattern recognition with Associative Memory (ASIC) Linear PCA-based track fit with FPGAs Associative Memory (AM) ASIC: the core processor of the pattern recognition stage. Evolution of the AMchip03 of SVT (CDF) Current prototype AMchip04 done and under testing: 65 nm technology (SVT chip was 180 nm) 8k patterns/chip (5k patterns/chip) Ternary logic for variable resolution (new feature) AMchip05 (FTK final chip candidate): 32k – 64k patterns Serial links

36. Further R&D (2014-) Interest in microchanneling (BaBar heritage, now ALICE, LHCb) Study of micro-machined substrates for cooling

37. 37 Stri-pixels for CCE measurements goal: compare CCE before/after irradiation – with MIPs or laser HV: wire-bonding to bias-tab read-out system: stripixel wire-bonded to pitch adapter of Beetle chip; read-out through Alibava system (1 at LPNHE, 1 in Geneva/CERN) HV distribution 3 stripixel sensors with different layout pitch adapterBeetle chip wire-bonding (CERN)