1. BITS Pilani Pilani Campus Pawan Sharma Lecture 26-28 05-03-2012 EEE /INSTR/CS F241 ES C263 Microprocessor Programming and Interfacing

2. BITS Pilani, Pilani Campus  String Instructions  Logical Instructions  IN/OUT instructions Last Lecture

3. BITS Pilani, Pilani Campus  Program Models  LOOP instructions  Signed multiplication and division  In/OUT instr  PUSH/POP Today’s Lecture

4. BITS Pilani, Pilani Campus Program Models MASM (Microsoft Assembler)

5. BITS Pilani, Pilani Campus MODELS  There are many models available to MASM Assembler ranging from Tiny to Huge  To designate a model use the.MODEL statement followed by the size of the memory system Ex:.MODEL TINY – enables the use of simplified segments TINY Model requires that all program and data fit into one 64K segment . DATA defines data segment .CODE defines code segment .STARTUP .EXIT

6. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956. model tiny.data DATA1 DB 23 DATA2 DW 9999h DATA3 DW 9999 ARRAY DW 01,02,03,04,05,06,07,08.code.startup MOV BX,DATA2 MOV CX,DATA3 MOV DATA1,BL MOV DL,DATA1 MOVDI,0001 H MOV AX, ARRAY [DI].exit end

7. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956.model tiny.DATA DATA1 DB 23H ARRAY DW 01,02,03,04,05,06,07,08.CODE.startup MOV AX, ARRAY MOV CL, DATA1 MOV BX, OFFSET ARRAY MOV AL,[BX].exit end

8. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Model TypeDescription TinyAll the data and code fit in one segment. Tiny programs are written in.COM which means the program must be originated at location 100H SmallContains two segments - One DS of 64k bytes and one CS of 64k bytes MediumContains one DS of 64kbyte and any number of CS for large programs CompactOne CS contains the program and any number of DS contains the data Largeallows any number of CS & DS HugeSame as large - but the DSs may contain more than 64k bytes each * Flat Model –Special type of Tiny Model for 32-bit

9. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956.MODEL SMALL; This statement is required before you can use other ;simplified segment directives.STACK ; Use default 1-kilobyte stack.DATA ; Begin data segment ; Place data declarations here.CODE ; Begin code segment.STARTUP ; Generate start-up code  ; Place instructions here.EXIT ; Generate exit code END

10. BITS Pilani, Pilani Campus  Used to repeat a series of instructions some number of times and are basically conditional jump instructions.  The no. of times, sequence is to be repeated is loaded in CX  Combines two operations in each instruction.  First, each time Loop instruction executes, CX automatically decrements by 1  Secondly, jump to a specified label if CX  0, and sometimes checks zero flag, after auto- decrement of CX LOOP

11. BITS Pilani, Pilani Campus  IF CX  0 execution will jump to destination, specified by a label in the instruction  If CX = 0 after auto dec, execution will go on to the next instruction after LOOP  Destination address is of type SHORT  LOOP affects no FLAGs

12. BITS Pilani, Pilani Campus Add a data in one block of memory with data in another block of memory using LOOP Size of block -100 words Y 1 =X 1 + Y 1 Y 2 =X 2 + Y 2 ………… Y n= =X n + Y n

13. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956.Model Tiny.data BLOCK1 DW 100 DUP(01) BLOCK2 DW 100 DUP(02) COUNTDW100.code.startup CLD MOV CX, COUNT MOV SI, OFFSET BLOCK1 MOV DI, OFFSET BLOCK2 X1: LODSW ADD AX, ES:[DI] STOSW LOOP X1.EXIT END

14. BITS Pilani, Pilani Campus LOOPE/LOOPZ ( LOOP while equal)  LOOP while CX  0 and ZF = 1  Each time the LOOP instr executes - CX decremented  If CX  0 & ZF = 1 execution will jump to destination specified  If CX = 0 after auto decrement or ZF = 0 execution will go to the next instruction  Destination address must be within -128 bytes to +127 bytes (short jump) Conditional LOOPs

15. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 MOV BX, OFFSET ARRAY DEC BX MOV CX, 100 NEXT: INC BX CMP [BX], 0FF H LOOPE NEXT On exit from loop: CX=0 and ZF=1  all elements are equal to FFH CX≠0  BX points to the first element that was not FFH CX=0 and ZF=0  last element was not FFH

16. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 LOOPNE/LOOPNZ Loop While CX  0 and ZF = 0 MOV BX, OFFSET ARRAY DEC BX MOV CX, 100 NEXT: INC BX CMP [BX], 0D H LOOPNE NEXT On exit from loop: CX=0 and ZF=0  0DH was not found in array CX≠0  BX points to the first element that contains 0DH CX=0 and ZF=1  the last array element was 0DH

17. BITS Pilani, Pilani Campus Multiply & Divide

18. BITS Pilani, Pilani Campus MUL SOURCE  Source times AL  Source times AX  Source can be a register or memory location  Result for Byte multiplication in AX  Result for Word multiplication in DX :AX  CF and OF zero if MSB/MSW zero  AF,PF,SF,ZF -undefined

19. BITS Pilani, Pilani Campus MUL BH MUL CX MUL BYTE PTR [BX] MOV AX, MULTIPLICAND _16 MOV CL, MULTIPLIER _8 MOV CH, 00 H MUL CX Multiplying byte with a word requires the byte’s MSB to be filled with 0’s

20. BITS Pilani, Pilani Campus.MODEL TINY.DATA MULTIPLICAND DW 2040 H MULTIPLIER DW 2000 H PRODUCT1 DW ? PRODUCT2 DW ?.CODE.STARTUP MOV AX, MULTIPLICAND MUL MULTIPLIER MOV PRODUCT1, AX MOV PRODUCT2, DX.EXIT END

21. BITS Pilani, Pilani Campus IMUL SOURCE  Signed Multiplication  Source times AL  Source times AX  Source can be a register or memory location  Result for Byte multiplication in AX  Result for Word multiplication in DX :AX  CF and OF zero if MSB/MSW zero ---- allows the user to detect and perhaps discard unnecessary leading zero’s in a result. If MSB and MSW contain part of the result, then both CF=OF=1  AF,PF,SF,ZF -undefined

22. BITS Pilani, Pilani Campus IMUL BH IMUL CX IMUL BYTE PTR [BX] MOV CX, MULTIPLICAND _16 MOV AL, MULTIPLIER _8 CBW IMUL CX

23. BITS Pilani, Pilani Campus DIV SOURCE Divides UNSIGNED WORD by a BYTE Divides UNSIGNED DWORD by a WORD  Word/Byte  Word in AX,  Byte in Register/Memory location  AL- quotient AH- reminder  DWORD/WORD  DWORD in DX : AX  Word in Register/Memory Location  AX- QuotientDX- Reminder All Flags undefined To divide a byte by a byte, put the dividend byte in AL and fill AH with 0’s

24. BITS Pilani, Pilani Campus IDIV SOURCE SIGNED WORD/BYTE SIGNED DWORD/WORD Word/Byte Dividend Word in AX, Divisor Byte in Register/Memory location AL- quotient AH- reminder DWORD/WORD Dividend DWORD in DX : AX Divisor Word in Register/Memory Location AX- QuotientDX- Reminder All Flags undefined- Sign of remainder same as dividend To divide a byte by a byte, put the dividend byte in AL and fill AH with copies of the sign bit from AL.

25. BITS Pilani, Pilani Campus IN Accumulator, PORT  Copy a data from a port to AL (if 8-bit port or I/O address is read) or AX (if 16-bit port or I/O address is addressed)  I/O ports are 8-bits in width so whenever a 16-bit port is accessed, two consecutive 8-bit ports are actually addressed.  Two formats possible  Fixed port (the 8-bit address of a port is directly specified in the instruction) and variable port ( the port address is loaded into the DX register used to address the I/O device, before the IN instruction) – IN AL, 00 H – IN AX, 20 H INPUT AND OUTPUT INSTRUCTIONS

26. BITS Pilani, Pilani Campus Port address appear on the address bus during I/O operation 8-bit address zero extended – IN AL, 06 H  Copies data from port and address appear as 0006 H on (A 0 to A 15 )  Other higher address undefined

27. BITS Pilani, Pilani Campus Variable Port Addressing allows transfer between AL, AX and a 16-bit port address available in DX DX can be changed by program control, giving a variable address. Does not affect flags. Advantage over fixed-port addressing. – MOV DX,0FF78H;initialize DX to point to port – IN AL, DX; input a byte from 8 bit port FF78H to AL – IN AX, DX; input a word from 16-bit port FF78H(LSB) ;and FF79H (MSB)

28. BITS Pilani, Pilani Campus OUT PORT, Accumulator  Copies a byte from AL or a word from AX to the specified port. Has two possible forms: fixed port and variable port.  OUT 05 H, AL  OUT 03 H, AX  MOV DX, 0FFF8H  OUT DX, AL  OUT DX, AX Fixed port variable port

29. BITS Pilani, Pilani Campus  Input a data from a port at address 05 H. Input data is a valid one digit BCD number. Use a lookup table to convert it into seven segment code. Output to port 50 H

30. BITS Pilani, Pilani Campus a b c d e f g h a b c d e f g h Seven segment display

31. BITS Pilani, Pilani Campus.Model Tiny.DATA TABLE DB 3F H, 06H, 5B H, 4F H, 66 H, 6D H DB 7D H, 07 H, 7F H, 67 H----common cathode configuration.CODE.STARTUP IN AL, 05 H LEASI, TABLE MOVBX,0 ADDBL,AL MOVAL,[SI+BX] OUT50 H,AL.EXIT END

32. BITS Pilani, Pilani Campus XLAT  Translate instruction used to translate a byte from one code to another code.  The instruction replaces a byte in the AL register with a byte pointed to by BX in a lookup table in memory.  Before using XLAT, the lookup table containing the values of new code is put in memory  Offset of the starting address of the table is loaded into BX  Byte to be translated is put in AL  To point to the byte in table, adds the contents of AL with BX to form a memory address in data segment  Copies the contents of this memory (BX + AL) into AL

33. BITS Pilani, Pilani Campus.Model Tiny.DATA TABLE DB 3F H, 06 H, 5B H, 4F H, 66 H, 6D H DB 7D H, 07 H, 7F H, 67 H.CODE.STARTUP IN AL, 05 H LEA BX, TABLE XLAT OUT50 H,AL.EXIT END

34. BITS Pilani, Pilani Campus PUSH and POP Instructions  Store and retrieve data from LIFO stack memory  Two bytes involved  Whenever data pushed into stack  MSB moves into memory [SP-1]  LSB moves into memory [SP-2]  Contents of SP register decremented by 2

35. BITS Pilani, Pilani Campus  Push source  Registers/Segment Register  Memory  Flag Register  PUSH AX;decrement SP by 2, copy AX to stack  PUSH BX  PUSH SI  PUSH WORD PTR[BX]; decrement SP by 2, copy word from ;memory in DS at [BX] to stack  PUSHF

36. BITS Pilani, Pilani Campus 70050 H 7004F H AH 7004E H AL 7004D H BH 7004C H BL 7004B H SIH 7004A H SIL 70049 H MEMH 70048 H MEML 70047 H FRH 70046 H FRL SP  SP-2[004E H ] 7004E H  AX SP  SP-2[004C H ] 7004C H  BX SP  SP-2[004A H ] 7004A H  SI SP  SP-2[0048 H ] 70048 H  MEM SP  SP-2[0046 H ] 70046 H  FLAGS SP:0050 H SS:7000 H

37. BITS Pilani, Pilani Campus POP  POP performs inverse of PUSH  Takes data from stack to general purpose register, memory or segment register  Data popped in 16 bits  First byte from stack to lower register  Second byte to higher address  SP = SP+2 – POP AX – POP CX – POP WORD PTR[BX] – POP CS is illegal

38. BITS Pilani, Pilani Campus Q: Set the TRAP flag without changing any of the other flags PUSHF MOV BP,SP INC BP OR [BP],01H POPF

39. BITS Pilani, Pilani Campus Subroutines

40. BITS Pilani, Pilani Campus CALL Instruction  CALL instruction in the main line program loads the Instruction pointer and in some cases also the Code Segment register with the starting address of the procedure  Next instruction fetched will be the first instruction of the procedure

41. BITS Pilani, Pilani Campus RET instruction at the procedure end, sends the execution back to the instruction after the CALL instruction in the main line program RET MAIN CALL Sub- Program

42. BITS Pilani, Pilani Campus CALL Stores the address of the instruction after CALL, into stack ( return address) near CALL or far CALL (IP saved) (CS and IP saved)  RET inst retrieves the next address after CALL  Back to IP or ( IP and CS)

43. BITS Pilani, Pilani Campus DIRECT WITHIN –SEGMENT- NEAR CALL  RELATIVE DISPLACEMENT  CALL LABEL  IP IP + d16 (signed displacement)‏ INDIRECT WITHIN SEGMENT- NEAR CALL  16-BIT IP REPLACED BY REGISTER / MEMORY LOCATION CONTENTS  CALL BP  CALL WORD PTR [BX]  IP reg16/mem16

44. BITS Pilani, Pilani Campus DIRECT INTERSEGMENT FAR CALL Both CS and IP needs to be changed CALL IPL IPH CSL CSH INDIRECT INTERSEGMENT FAR CALL Two words taken From Memory First word  IP, Second word  CS CALL DWORD PTR [BX]

45. BITS Pilani, Pilani Campus Instruction Timing and Delay Loops

46. BITS Pilani, Pilani Campus Subroutine commonly used is delay subroutine Software delays using LOOP Delay required = 1ms =1000µs 8086 running on 5MHz clock- Each cycle is 0.2µs  Total of 5000 clock cycles required=C T Introduce the instructions: MOV CX,N 4 Cycles X1: NOP 3 Cycles NOP 3 Cycles LOOP X1 17 or 5 Cycles

47. BITS Pilani, Pilani Campus Overhead = C O = 4 Number of cycles/loop = C L = 3+3+17 = 23 Number of times the loop runs = N C T = C 0 + N*C L – 12 5000 = 4 + N*23 –12  N = 218

48. BITS Pilani, Pilani Campus Write an ALP that takes 100 data samples from input port, at intervals of 1ms and masks the upper four bits of each sample and puts each masked sample in successive memory locations in ARRAY –using subroutines

49. BITS Pilani, Pilani Campus In Assembly language programming, Procedures (subroutines) begin with PROC directive and ends with ENDP directive PROC directive is followed by the type of procedure: NEAR or FAR CALL instruction links to the procedure RET instruction returns from the procedure

50. BITS Pilani, Pilani Campus CALL SUMS _____ SUMS PROC NEAR ADD AX, BX ADD AX, CX ADD AX, DX RET SUMS ENDP

51. BITS Pilani, Pilani Campus.Model Tiny.data res db100 dup(0) stack dw100 dup(?) ; get aside 100 words for stack top_stack label word ; give name to next location after last word in stack.code.startup lea sp, top_stack ; initialize stack pointer leadi, res movcx,100 x1:inal, 05 h callmask call delay loopx1.exit

52. BITS Pilani, Pilani Campus call – 19 ret – 16 Overhead = CO = 4 +19+16 No. of cycles/loop CL = 3+3+17 = 23 No. of times the loop runs = N CT = C0 + N*CL – 12 5000 = 39 + N*23 –12  N = 217 Maskprocnear andal,0f h stosb ret Maskendp Delayprocnear movcx,217 x2: nop nop loop x2 ret Delayendp end