1. A Time-To-Digital Converter (TDC) Harley Cumming Lisa Kotowski 1

2. The Problem How to measure very small time intervals accurately? 2 Event 1 Event 2 20 ns Conventional Approach: Use A Clock -100 ps period for 1% accuracy - Requires 10 GHz clock Time

3. The Solution How to measure very small time intervals accurately? 3 Event 1 Event 2 20 ns Time Better Approach: Use a longer time scale -Charge small capacitor for event duration -Charge second capacitor slower -Time for voltages to be equal

4. 4 Concept Input Voltage Ramp C1 20 nsA*20 ns I Comparison Voltage Ramp A*C1 I Charge Time To FPGA

5. Applications Time of Flight ▫Mass Spectroscopy ▫Medical Devices Laser Distance Meters ▫Police Radar Guns ▫Golf Range Finders ▫Measuring Speed of Light 5 Figure [1]: How a police radar gun determines the speed of a moving vehicle.

6. Design Goals Measure pulses across multiple time scales: ▫100 ps ▫1 ns ▫10 ns ▫100 ns Maximum time of 100ns Output results to 7-segment display 6

7. Design Considerations Timing critical paths ▫Voltage ramp controls ▫FPGA Counter Logic Component delay ▫MOSFET turn-on/off time ▫Logic gate 7

8. Operation 8 Time

9. Operation 8 Measurement Event Occurs Time

10. Operation 8 Measurement Event Occurs Comparison Voltage Ramps Trigger Time

11. Operation 8 Measurement Event Occurs Comparison Voltage Ramps Trigger Measure Comparison Charge Time Time

12. Operation 8 Measurement Event Occurs Comparison Voltage Ramps Trigger Time displayed Time Measure Comparison Charge Time

13. Overall Design 9 Input Control Logic Stop Start

14. Overall Design 9 Input Control Logic Input Voltage Ramp Stop Start Input Capacitor Voltage

15. Overall Design 9 Input Control Logic Input Voltage Ramp Stop Start FPGA Input Capacitor Voltage

16. Overall Design 9 Input Control Logic Input Voltage Ramp Comparison Start Comparison Control Logic Comparison Stop Stop Start FPGA Input Capacitor Voltage

17. Overall Design 9 Input Control Logic Input Voltage Ramp Comparison Voltage Ramps Comparison Start Comparison Control Logic Comparison Stop Stop Start FPGA Input Capacitor Voltage Comparison Capacitor Voltages

18. FPGA Design 10 Input Capacitor Voltage (Blue)

19. FPGA Design 10 Input Capacitor Voltage (Blue) Comparison Capacitor Voltages (Red)

20. FPGA Design 10 Input Capacitor Voltage (Blue) Comparison Capacitor Voltages (Red) Comparators (Implemented by IBUFDS)

21. FPGA Design 10 Input Capacitor Voltage (Blue) Comparison Capacitor Voltages (Red) Comparators (Implemented by IBUFDS) Counter Control

22. FPGA Design 10 Input Capacitor Voltage (Blue) Comparison Capacitor Voltages (Red) Comparators (Implemented by IBUFDS) Counter Control 16 Bit Binary Ripple Counter

23. FPGA Design 10 Input Capacitor Voltage (Blue) Comparison Capacitor Voltages (Red) Comparators (Implemented by IBUFDS) Counter Control 16 Bit Binary Ripple Counter Display Logic To Display

24. FPGA Design 10 Input Capacitor Voltage (Blue) Comparison Capacitor Voltages (Red) Comparators (Implemented by IBUFDS) Counter Control 16 Bit Binary Ripple Counter Display Logic To Display State Machine Board Level Control Logic Inputs from board

25. FPGA Results 11 16 ns simulated interval

26. FPGA Results 11 16 ns simulated interval

27. FPGA Results 11 16 ns simulated interval

28. FPGA Results 12 72 ns simulated interval

29. FPGA Results 12 72 ns simulated interval

30. FPGA Results 12 72 ns simulated interval

31. Complications Unable to order a PCB Circuit implemented on SMT breadboard ▫Added Capacitance and Delays ▫Possible Hardware issues Had to reorder some parts due to space- limitations ▫Original parts too small for SMT breadboard 13

32. Tasks Completed FPGA Core Built and Simulated ▫Synthesizes ▫Timing requirements met ▫Successfully measures and displays simulated times SMT Breadboard Complete ▫All parts placed and wired ▫Short checks complete Begin Testing 14

33. Tasks Remaining Complete Integration ▫Successfully measure event ▫Compare observed and expected results 15

34. Acknowledgments Professor Varner for design review and implementation ideas Dr. Cooney for all the help and support he provided us in the last minute rush to completion IDL Staff for assistance with implementation 16

35. Questions? 17