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Presentation 2: A More Detailed Look Advanced VLSI Design (ECE 1193) Kent Nixon, Tom Nason, Enes Eken, and Christopher Lukas January 17, 2013
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Department of Electrical & Computer Engineering Project Goal Create a simulatable clone of the original Gameboy system using Mentor Graphics CAD tools.
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Department of Electrical & Computer Engineering Gameboy Specifications CPU: Custom 8-bit Sharp LR35902 core at 4.19MHz –Similar to both Intel 8080 and Zilog Z80 RAM: 8 kB internal S-RAM (can be extended up to 32 kB) Video RAM: 8 kB internal ROM: On-CPU-Die 256-byte bootstrap –256 KB, 512 KB, 1 MB, 2 MB, 4 MB and 8 MB cartridges Sound: 2 square wave generators, 1 PCM 4-bit wave sample (64 4-bit samples played in 1x64 bank or 2x32 bank) channel, 1 noise generator, and one audio input from the cartridge Display: Reflective STN LCD 160 × 144 pixels
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Department of Electrical & Computer Engineering
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CPU (+ GPU + Audio) LCD VRAM Main RAM Cartridge (MC + ROM + RAM) Audio System Input Buttons Serial
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Department of Electrical & Computer Engineering LCD Inputs: Data[1:0], Clock, Control, Outputs: Vsync, Hsync Unknown: DataLatch, AltSigl(?) Probably a lot of interesting things going on in here –However, not sure if creating an LCD is within the scope of the course Can be represented as what is essentially a bitmap –Would be easy to print out
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Department of Electrical & Computer Engineering VRAM and Main RAM 8 kB blocks of memory Not shown in any of the schematics, but there must be some sort of synchronization signal
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Department of Electrical & Computer Engineering Game Cartridge Inputs: Address[15:0], Clock, Read, Write, Chip Select Outputs: Vin (audio wave) Input/Outputs: Data[7:0], Reset Own onboard memory controller to handle access to onboard ROM and RAM from Gameboy CPU –Like a whole extra system Many different types of cartridge (at least 5) –We plan on implementing just one type
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Department of Electrical & Computer Engineering Inside of the Cartridge How does it look like? Kinds of Cartridges - ROM + MBC + RAM+BATTERY - ROM +RAM + BATTERY - ROM + RAM - ROM
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Department of Electrical & Computer Engineering Which one is the best? Of course the easiest one Just a 32KB EPROM
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Department of Electrical & Computer Engineering A Simple Implementation of This Idea Guys from Karlsruhe University
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Department of Electrical & Computer Engineering Audio System Inputs: Audio[1:0] Basically an amplifier and a MUX to select between the Gameboy (GB) speaker or stereo headsets Signal is already analog (or a close representation of such) before reaching this point
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Department of Electrical & Computer Engineering Input Buttons Inputs: ColSel[1:0] Outputs: Pressed[3:0] A single 2x4 contact array –GB CPU scans 1 column at a time to register button presses –Decoded in software, but stored in a dedicated register A► B◄ Select▲ Start▼ ColSel[1] ColSel[0] Pressed[3] Pressed[2] Pressed[1] Pressed[0]
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Department of Electrical & Computer Engineering Serial Communications Reads and writes at the same time –Novel solution to minimize shift registers How to detect if we are master or slave?
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Department of Electrical & Computer Engineering Slave Master CPU (+ GPU + Audio Processors) Memory Controller CPU Logical Core LCD Controller (GPU) ROM On-Chip RAM Interrupt Controller Data Buffer Address Buffer Sprite RAM Audio Controller Clock Audio System Cartridge + Main RAM Input Buttons Serial I/O LCD Cartridge Serial Control
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Department of Electrical & Computer Engineering CPU Logical Core Accesses peripherals via MMIO –16-bit addresses Loads from a known memory address at boot to get the bootstrap code Can be interrupted (duh) 8 registers + PC + SP RISC or CISC? Cache?
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Department of Electrical & Computer Engineering LCD Controller Seems to handle all of the heavy lifting of what to print to the LCD Has access to sprite memory and VRAM Outputs control signals and actual pixel-by-pixel data Controlled indirectly by CPU via register values Primitive GPU?
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Department of Electrical & Computer Engineering Memory Controller Absolute animal –Connects to pretty much everything in the system Arbitrates memory access and decodes logical>physical addresses
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Department of Electrical & Computer Engineering Interrupt Controller 4 internal, 1 external –Internal LCD Display Vertical Blanking Status Interrupts from LCDC (4 modes) Timer Overflow Interrupt Serial Transfer Completion Interrupt –External End of Input Signal for ports P10-P13 CPU can mask when handling others –Accomplished in CPU or in controller? Cause PC jumps to known locations that jump to the handler
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Department of Electrical & Computer Engineering Address and Data Buffers Hold 16-bit address and 8-bit data being sent to or received from the cartridge or the main RAM –Calculated and handled by memory controller Must need some sort of synchronizing signal
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Department of Electrical & Computer Engineering ROM 256 Bytes Holds the bootstrap program for the Gameboy –Scrolling Nintendo logo and “po-ling” sound
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Department of Electrical & Computer Engineering On-Chip RAM 127 Bytes Used for the stack
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Department of Electrical & Computer Engineering Sprite RAM 140 Bytes Used to store sprites, up to 40 2 different sizes of sprites –Setting register values in the LCD controller changes how they are accessed Accessed by both LCD Controller and CPU
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Department of Electrical & Computer Engineering Audio Controller Audio Control Registers Audio Memory Quadrangular with Sweep and Envelope Quadrangular with Envelope Wave from RAM White Noise with Envelope Memory Controller Audio Synthesizer Audio System Cartridge No idea what these do
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Department of Electrical & Computer Engineering Audio Details Sweep functionality: f(t) = f0 + ((f1-f0)/t1)*t t = array of times to calculate f0 = beginning frequency (f1, t1) = point of intersection for sweep Frequency audio output: register value = 2048 - ( 131072 / f ) f = 131072 / ( 2048 - gbRegisterVal ) Stereo Sound Four functions, mixed separately to output
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Department of Electrical & Computer Engineering Responsibilities Team Member Technical Responsibilities Corporate Responsibilities Kent W. Nixon Serial, Memory Controller Color Selection Tom NasonTBDBusiness Card Design Enes EkenCartridgePlay Testing Christopher LukasAudio Human Resource Management
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Department of Electrical & Computer Engineering Plans for Next Week Further refine our understanding of the GB architecture and precisely what each of the subsystems involve –Start making interface hierarchies in HDL Designer Determine who wants or wants not to work on certain parts Split group into 2 groups of 2 and assign responsibilities Coordinate time outside of classes each group of two can meet and work through their part of the project together
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