1. LECTURE VI USER DEFINED PRIMITIVES GATE-LEVEL MODELING

2. A useful tool in Verilog is UDP (User Defined Primitive). This primitive actually defines a combinational circuit whose function is described in Sum of Products form tabular form. It can have multiple inputs but only one output. It begins with the keyword primitive followed by its name and the ports used. Note: the output port must be listed first. The output of the circuit being defined is then specified using the keyword ouput The inputs are defined next using the keyword input Next comes the truth table for the circuit beginning with the keyword table Be sure to account for every possible combination of the inputs within the table Conclude the table with the keyword endtable Conclude the User Defined Primitive module with the keyword endprimitive

3. Example of a UDP:

4. The UDP is not a module in and of itself so in order for it to be used, a module must be written in which it is instantiated. Please note that the ports in this module are used to pass information to and from the UDP and, therefore, must be named differently than those in the UDP. Also remember that Verilog is case sensitive.

6. The circuit that this module demonstrates is shown here and on page 118, Fig 3.37

7. This represents the simulation with three different inputs for a,b,c,d.