1. PACKAGE FABRICATION TECHNOLOGY Submitted By: Prashant singh

2. INTRODUCTION Packaging is ‘every technology’ required between the IC and the system. Packaging is basically done at three levels- chip level, board level and system level. The grouping or combining of components, integrated circuits or chips into a unit and through holes on a multilayer circuit board. Purpose of packaging →To provide electrical connections. →Extend the chip electrode pitch to the next level of packaging. →To protect the chip from mechanical & environmental stress. →To provide a proper thermal path for the heat that the chip dissipates.

3. INTRODUCTION Major functions of Packaging.  Signal distribution  Power distribution  Heat dissipation (cooling)  Protection (mechanical, chemical, electromagnetic)

4. TYPES OF PACKAGE FABRICATION TECHNOLOGIES The die will be packaged in either a Through-Hole or Surface Mount package type. The package technology will be of two type: → Refractory ceramic technology(for mature product where low costs is critical but hermetic seal is still required) → Molded plastic technology(for matured products where cost is important)

5. Contd….  On the basis of Package-to-Board attachment: 1.In Surface mount package: → Distance between leads are reduced. → Over all package size reduced. → Require skilled worker and expensive tools. 2.In Through-hole package: → Refers to the mounting scheme that involves the use of leads on the components. → That are inserted into holes drilled in (PCB) and soldered to pads on the opposite side either by manual assembly by hand placement.

6. Contd… 3. SINGLE CHIP PACKAGES → supports a single microelectronic device → low cost 4. MULTICHIP PACKAGES → If the package contains more than one active device. → high performance → packaging at very low cost.

7. Contd…  On the basis of chip-to-package interconnection:  Wirebond  Tap automated bonded(TAB)  Flip Chip  Chip on board

9. Wirebond The process of providing electrical connection between the silicon chip and the external leads of the semiconductor device using very fine bonding wires. Wire bonding is generally considered the most cost- effective and flexible interconnect technology. The wire used in wirebonding is usually made either of gold (Au) or aluminum (Al)

10. Tap automated bonded(TAB) It is the process of mounting a die on a flexible tape made of polymer material, such as polyimide. The mounting is done such that the bonding sites of the die, usually in the form of bumps or balls made of gold or solder, are connected to fine conductors on the tape, which provide the means of connecting the die to the package or directly to external circuits.

11. Flip Chip In flip-chip joining there is only one level of connections between the chip and the circuit board. The length of the electrical connection between the chip and substrate can be minimized by placing solder bumps on the die. Advantages: Smaller size Increased functionality Improved performance Low cost

12. Disadvantages: · Challenge for PCB technology as pitches become very fine and bump counts are high. · For inspection of hidden joints an X-ray equipment is needed. · Weak process compatibility with SMT. · Handling of bare chips is difficult. · High assembly accuracy needed. · With present day materials underfilling process with a considerable curing time is needed. · Low reliability for some substrates. · Repairing is difficult or impossible

13. Chip on board It refers to the semiconductor assembly technology wherein the microchip or die is directlymounted on and electrically interconnected to its final circuit board, instead of undergoing traditional assembly or packaging as an individual IC. simplifies the over-all process of designing and manufacturing. The general term for COB technology is actually 'direct chip attachment.

14. Advantages: 1) reduced space requirements 2) reduced cost 3) better performance due to decreased interconnection lengths and resistances 4) higher reliability due to better heat distribution and a lower number of solder joints 5) shorter time-to-market

15. Comparision

16. 3-D Packaging Technology A 3-D IC is a chip in which two or more layers of active electronics component are integrated both vertically and horizontally into a single circuit. It saves spaces. This is also known as system in packages(SIP)

17. There are four ways to build: Monolithic: Electronic components and their connections are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through- silicon vias. Wafer-on-Wafer: Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D Ics. Die-on-Wafer: Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. Die-on-Die: Electronic components are built on multiple dice, which are then aligned and bonded.

18. Advantage:

19. REFRENCES http://www.siliconfareast.com

20. Thank you