1. 3-1 MKE1503/MEE10203 Programmable Electronics Computer Engineering Department Faculty of Electrical and Electronic Universiti Tun Hussein Onn Malaysia CPLD and FPGA Architectures

2. 3-2 Definitions  Field Programmable Device (FPD): — a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured “in-system”. Another name for FPDs is programmable logic devices (PLDs). Source: S. Brown and J. Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design and Test of Computer, 1996

3. PLDs 16V8 (20 Pins) can have 16 inputs (max) and/or 8 outputs (marcrocells) has 32 inputs to each of the AND gates (product terms) 22V10 (24 pins) can have 22 inputs and/or 10 outputs (max) has 44 inputs to each of the AND gates How about a “128V64” for larger applications? It will be slower and will more wasted silicon space Solution? Use CPLDs Rissacher EE365Lect #14

4. GAL16V8 (review seq_1.ppt) Each output is programmable as combinational or registered Also has programmable output polarity And Plane The OR gates XOR gates to make inverting or non-inverting buffer XOR gates to make inverting or non-inverting buffer Rissacher EE365Lect #14

5. 3-5 Classifications of Early Programmable Logic  PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND- plane and an OR-plane, where both levels are programmable  PAL — a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane  SPLD — refers to any type of Simple PLD, usually either a PLA or PAL  CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip.  FPGA — a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity.

6. 3-6 PLA

7. 3-7 PLA

8. 3-8 PAL Programmable AND Plane X Y O1O2O3O4 Fix OR Plane

9. 3-9 PAL with Logic Expanders Programmable AND Plane Logic expanders Fix OR Plane ?

10. 3-10 PLA v.s. PAL  PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs.  Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation delay.  By using fix OR gates, PALs are cheaper and faster than PLAs.  Logic expanders increase the flexibilities of PALs, but result in significant propagation delay.  PALs usually contain D flip-flops connected to the outputs of OR gates to implement sequential circuits.  PLAs and PALs are usually referred to as SPLD.

11. 3-11 CPLD  A CPLD comprises multiple PAL-like blocks on a single chip with programmable interconnect to connect the blocks.  CPLD Architecture PAL-like block PAL-like block PAL-like block PAL-like block I/O block Programmable interconnect

12. A General CPLD structure A collection of PLDs on a single chip with Programmble interconnects Rissacher EE365Lect #14

13. Who makes the CPLDs? Manufacturer CPLD Products URL Altera MAX 5000, 7000 & 9000 www.altera.com Altmel ATF & ATV www.atmel.com Cypress FLASH370, Ultra37000 www.cypress.com Lattice ispLSI 1000 to 8000 www.latticesemi.com Philips XPLA www.philips.com Vantis MACH 1 to 5 www.vantis.com Xilinx XC9500 www.xilinx.com Manufacturer CPLD Products URL Altera MAX 5000, 7000 & 9000 www.altera.com Altmel ATF & ATV www.atmel.com Cypress FLASH370, Ultra37000 www.cypress.com Lattice ispLSI 1000 to 8000 www.latticesemi.com Philips XPLA www.philips.com Vantis MACH 1 to 5 www.vantis.com Xilinx XC9500 www.xilinx.com Let’s takes a look at this Rissacher EE365Lect #14

14. 3-14 Altera MAX CPLD LAB I/O Cell Chip-wide interconnect Altera MAX chip LAB (Logic Array Block) LA (local array) Macroccell  Each LAB contains 16 macrocells

15. 3-15 Macrocell of Altera MAX CPLD 5 114 Product term select Programmable inversion DQ M Local Array 3 Clock, clear, preset, enable System clockSystem enable Parallel expander To next macrocell Macrocell MAX 9000 has 33 inputs, can you explain why LA has 114 inputs? OUT

16. FPGAs Historically, FPGA architectures and companies began around the same time as CPLDs FPGAs are closer to “programmable ASICs” -- large emphasis on interconnection routing –Timing is difficult to predict -- multiple hops vs. the fixed delay of a CPLD’s switch matrix. –But more “scalable” to large sizes. FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD. Rissacher EE365Lect #14

17. 3-17 FPGA  FPGA consists of an array of programmable basic logic cells surrounded by programmable interconnect.  FPGA Structure Logic cell Programmable interconnect I/O Cell

18. 3-18 FPGA v.s. CPLD  Capacitance SPLDsCPLDsFPGAs Equivalent gates0 ~ 200200 ~ 12,0001000 ~ 1,000,000  Applications CPLDs FPGAs 1.Implement random glue logics or Replace circuits previously implemented by multiple SPLDs 2.Circuits that can exploit wide AND/OR gates, and do not need a very large number of flip-flops are good candidates for implementation in CPLDs. 1.FPGAs can be used in various applications: prototyping, FPGA-based computers, on-site hardware re- configuration, DSP, logic emulation, network components, etc.

19. Problems common to CPLDs and FPGAs Pin locking –Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout. –Locking too early may make the resulting circuit slower or not fit at all. Running out of resources –Design may “blow up” if it doesn’t all fit on a single device. –On-chip interconnect resources are much richer than off-chip; e.g., barrel-shifter example. –Larger devices are exponentially more expensive. Rissacher EE365Lect #14