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Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Performances of the Front End Electronics for the HADES RPC wall in.

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Presentation on theme: "Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Performances of the Front End Electronics for the HADES RPC wall in."— Presentation transcript:

1 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Performances of the Front End Electronics for the HADES RPC wall in last 12 C beam Daniel Belver - University of Santiago de Compostela, Spain For the HADES RPC group DIRAC phase1

2 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 OUTLINE The HADES spectrometer. The RPCs Front-End Electronics. FEE architecture. Daughterboard design (DBO Step5). Motherboard design (MBO v3). Low voltage board. DAQ: TDC Readout Board (TRB). In 12 C+Be-Nb beam results (GSI, Oct07). Summary and conclusions.

3 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 HADES High Acceptance Di-Electron Spectrometer HADES (GSI, Darmstadt) is a spectrometer designed to analyse the properties of the nuclear matter in NN collisions at kinetic energies from 1-2 A.GeV and its upgrade up to 8 A.GeV. HADES back viewHADES vertical cut RPCs Wall Beam low angles

4 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Motherboard (MBO) + Daughterboard (DBO) philosophy. MBO 32 channels / 8-layers board (262cm 2 ). - Regulators, thresholds DAQs, test signals, trigger logic. DBO 4 channels / 6-layer board (22.5cm 2 ). - 1 amplification stage, LVDS digital output and QtoW implemented. TDC Readout Board (TRB) for acquisition. Power supply boards for +3.3V, +5V, -5V. DBOs MBOs RPC MBO DBO RPC FEE architecture (I)

5 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE architecture (II) MBDB RPC signals RPC cells Front End Ethernet TRB Data acquisition system 5V,-5V,3.3V DC-DC converter 48V 5 3.3 -5 Commercial power supply Low voltage system Trigger Trigger

6 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE architecture (II) MBDB RPC signals RPC cells Front End Ethernet TRB Data acquisition system 5V,-5V,3.3V DC-DC converter 48V 5 3.3 -5 Commercial power supply Low voltage system Trigger Trigger

7 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE architecture (II) MBDB RPC signals RPC cells Front End Ethernet TRB Data acquisition system 5V,-5V,3.3V DC-DC converter 48V 5 3.3 -5 Commercial power supply Low voltage system Trigger Trigger

8 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE architecture (II) MBDB RPC signals RPC cells Front End Ethernet TRB Data acquisition system 5V,-5V,3.3V DC-DC converter 48V 5 3.3 -5 Commercial power supply Low voltage system Trigger Trigger

9 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE architecture (II) MBDB RPC signals RPC cells Front End Ethernet TRB Data acquisition system 5V,-5V,3.3V DC-DC converter 48V 5 3.3 -5 Commercial power supply Low voltage system Trigger Trigger

10 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE side connected to the RPC cells. Time and charge codified in a single digital LVDS signal, using QtoW. Low power consumption, ≈ 400mW/ch (DBO+MBO channel). Arrival time (ToF measurement)  Leading edge. Charge of RPC signals  Pulse width (QtoW measurement). Daughterboard (DBO) v5.0 width~charge Arrival time

11 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Analog stage PHILIPS BGM1013 amp (35.5dB,1GHz) TI OPA690 amp for QtoW Digital stage MAX9601 dual PECL discriminator: latch enable used for cut/shape the output pulse TI SN65LVDS100 PECL-LVDS converter PHILIPS BFT92 PNP wideband (5 GHz) transistor for multiplicity trigger sum DBO v5.0: one channel logic

12 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 LE LE/ Latch Enable is used like another comparator working when 2 digital levels cross through. DBO: Latch Enable configuration MAXIM Comparator

13 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE side connected to DBOs  interfaces DB with DAQ system (TRB). MBO provides support to 32 channels (8 DBOs) and 12 channels (3 DBOs) for short MBOs. Motherboard v3.0 (MBO) 1 full sector  12x8+4x3 MBOs=108 DBOs.

14 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Delivers the timing-signals from 8 DBOs to the TDC Readout board (TRB). Supply stable voltages to the DBOs  +5V,-5V,+3.3V. Combines the 32 multiplicity signals coming out from the DBOs to provide a low level trigger signal. Allocates DAQs for the threshold voltages on the DBOs. Other issues: test signals distribution, LVDS repeaters, interface for DAQ programming. MBO v3.0: schematic logic

15 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Multiplicity trigger Trigger is based on a multi-step analogue sum of the trigger outputs of all channels. Trigger summing is done sequentially in DBOs, MBOs and Trigger Units. MB DB

16 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Low voltage board is based on switching DC-DC converter modules with filters at inputs and outputs: - Input: +48V  Outputs: +5V, -5V, +3.3V. - Prepared for current and voltage monitoring. - Space saving (~20x15cm 2 =300cm 2 ). - 1 board feeds ½sector = 6MBOs + 2 short MBOs. - Time resolution is the same as with linear PS. Low voltage boards

17 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 TRB (TDC Readout Board) 128 multihit TDC channels (CERN’s HPTDC) Computing power: FPGA+DSP Control: ETRAX single chip computer + UNIX Comunications: Ethernet+optical link (2Gbit/s) TRB and DAQ (by GSI electronics group) High speed data acquisition based on the HPTDC ASIC.

18 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 TRB and DAQ TRB (TDC Readout Board) 128 multihit TDC channels (CERN’s HPTDC) Computing power: FPGA+DSP Control: ETRAX single chip computer + UNIX Comunications: Ethernet+optical link (2Gbit/s) (by GSI electronics group) High speed data acquisition based on the HPTDC ASIC.

19 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 TRB (TDC Readout Board) 128 multihit TDC channels (CERN’s HPTDC) Computing power: FPGA+DSP Control: ETRAX single chip computer + UNIX Comunications: Ethernet+optical link (2Gbit/s) TRB and DAQ (by GSI electronics group) High speed data acquisition based on the HPTDC ASIC.

20 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 TRB (TDC Readout Board) 128 multihit TDC channels (CERN’s HPTDC) Computing power: FPGA+DSP Control: ETRAX single chip computer + UNIX Comunications: Ethernet+optical link (2Gbit/s) TRB and DAQ (by GSI electronics group) High speed data acquisition based on the HPTDC ASIC.

21 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 TRB and DAQ (by GSI electronics group) 1 RPC full sector 3 TRBs + 1 TRB 12 MBOs 4 shortMBOs 96 DBOs 12 DBOs Actual TRB board design

22 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 LV 48VDC TRBs MBOs MBs DBs Experimental setup in 12 C beam miniMBOs

23 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 2 full equipped MBOs (2x8 DBOs connected to RPC cells). Test signals sent at the same time to even and odd channels. ToF thresholds at minimum possible value (-15mV). Results with test signals (I) ToF threshold=-15mV Time resolution FEE chain ≈ 40ps/ch (DBO+MBO+TRB) ≈40ps Time resolution FEE ≈ 15ps/ch (DBO+MBO)

24 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 2 full equipped MBOs (2x8 DBOs connected to RPC cells). Test signals were sent only at half of the channels. ToF thresholds at minimum possible value (-15mV). Results with test signals (II) ToF threshold=-15mV

25 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 In beam: time resolution ToF threshold=-50mV Time resolution FEE+RPC ≈ 75ps/ch Time difference (ps) σ ch =106ps Uncorrected Time difference (ps) σ ch =75ps Slewing correction 12 full equipped MBOs (12x8 DBOs connected to RPC cells). Minimum ToF thresholds -40mV for all channels connected to RPCs. HV=5600V-6000V.

26 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 QtoW left side QtoW measurements (I) QtoW right side ToF threshold=-50mV QtoW spectrums for one cell streamers

27 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 QtoW measurements (II) ToF threshold=-50mV QtoW right vs left sides of one cell Streamer avalanche example

28 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 LF LB CF CB RF RB Average number of pulses in each channel per trigger event. In beam behaviour LF LB CF CB RF RB RPC detector in final position inside the HADES spectrometer. All MBOs full equipped.

29 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE features: - Motherboard-Daughterboard arrangement. Moderate low power consumption, ≈ 400mW/ch. - Average FEE time resolution of 15ps/channel (DBO+MBO). - Average full FEE time resolution of 40 ps/channel (DBO+MBO+TRB). - TRB board for acquisition. Stable operation under beam conditions: - Average full system time resolution of 80 ps/channel. - Good behaviour for QtoW in charge measurements. - Integration in HADES demonstrated: mechanical, electromagnetic, software. - Low voltage system already integrated. Summary & Conclusions

30 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Thanks for your attention

31 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Back up

32 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 - HADES high multiplicity experiment need a new detector covering the small angle region for low level triggers and electron identification. - Main requirements: Time resolution below 100 ps. Charge measurement for timing corrections. Working rate ~600 Hz/cm 2 Crosstalk as small as possible. HADES RPC WALL GOAL Design in Paulo’s talk!

33 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 RPC WALL DESIGN Geometric acceptance close to 100% 1 sector  ~100cells x 2layers=200 cells Shielded cells: crosstalk<1% RPC double layer 6 sectors  ~1200 cells LeftCenterRight ~200 cells

34 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 In beam: detector position ToF threshold=-50mV Position all cells LF LB CF CB RF RB Position one cell 12 full equipped MBOs (12x8 DBOs connected to RPC cells). Minimum ToF thresholds -40mV for all channels connected to RPCs. HV=5600V-6000V. RPC detector in final position inside the HADES spectrometer.

35 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Efficiency measurements

36 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 FEE functionality tests MB: - Using WK Tester - Test signals arrival to DB - Thresholds settings - MB-DB lines connectivity No important failures found DB: - Using TRB - Time resolution measurements Summary: - 95 boards loaded ( = 380 channels) - 83 fully working - 11 with some channels dead - 1 board useless - 362 channels working - 332 (87%) connected to RPC cells

37 Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Time resolution (preliminary) 85.1 ps 74.9 ps

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