1. CSE477 L19 Timing Issues; Datapaths.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 19: Timing Issues; Introduction to Datapath Design Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477www.cse.psu.edu/~mji www.cse.psu.edu/~cg477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

2. CSE477 L19 Timing Issues; Datapaths.2Irwin&Vijay, PSU, 2003 Review: Sequential Definitions  Use two, level sensitive latches of opposite type to build one master-slave flipflop that changes state on a clock edge (when the slave is transparent)  Static storage l static uses a bistable element with feedback to store its state and thus preserves state as long as the power is on -Loading new data into the element: 1) cutting the feedback path (mux based); 2) overpowering the feedback path (SRAM based)  Dynamic storage l dynamic stores state on parasitic capacitors so the state held for only a period of time (milliseconds); requires periodic refresh l dynamic is usually simpler (fewer transistors), higher speed, lower power but due to noise immunity issues always modify the circuit (by adding a feedback loop on the output) so that it is pseudostatic

3. CSE477 L19 Timing Issues; Datapaths.3Irwin&Vijay, PSU, 2003 Timing Classifications  Synchronous systems l All memory elements in the system are simultaneously updated using a globally distributed periodic synchronization signal (i.e., a global clock signal) l Functionality is ensure by strict constraints on the clock signal generation and distribution to minimize -Clock skew (spatial variations in clock edges) -Clock jitter (temporal variations in clock edges)  Asynchronous systems l Self-timed (controlled) systems l No need for a globally distributed clock, but have asynchronous circuit overheads (handshaking logic, etc.)  Hybrid systems l Synchronization between different clock domains l Interfacing between asynchronous and synchronous domains

4. CSE477 L19 Timing Issues; Datapaths.4Irwin&Vijay, PSU, 2003 Review: Synchronous Timing Basics  Under ideal conditions (i.e., when t clk1 = t clk2 ) T  t c-q + t plogic + t su t hold ≤ t cdlogic + t cdreg  Under real conditions, the clock signal can have both spatial (clock skew) and temporal (clock jitter) variations l skew is constant from cycle to cycle (by definition); skew can be positive (clock and data flowing in the same direction) or negative (clock and data flowing in opposite directions) l jitter causes T to change on a cycle-by-cycle basis DQ R1 Combinational logic DQ R2 clk In t clk1 t clk2 t c-q, t su, t hold, t cdreg t plogic, t cdlogic

5. CSE477 L19 Timing Issues; Datapaths.5Irwin&Vijay, PSU, 2003 Sources of Clock Skew and Jitter in Clock Network PLL 1243567 clock generation clock drivers power supply interconnect capacitive load capacitive coupling temperature  Skew l manufacturing device variations in clock drivers l interconnect variations l environmental variations (power supply and temperature)  Jitter l clock generation l capacitive loading and coupling l environmental variations (power supply and temperature)

6. CSE477 L19 Timing Issues; Datapaths.6Irwin&Vijay, PSU, 2003 Positive Clock Skew DQ R1 Combinational logic DQ R2 clk In t clk1 t clk2 delay T T +   > 0  + t hold T : t hold : 1234  Clock and data flow in the same direction

7. CSE477 L19 Timing Issues; Datapaths.7Irwin&Vijay, PSU, 2003 Positive Clock Skew DQ R1 Combinational logic DQ R2 clk In t clk1 t clk2 delay   > 0: Improves performance, but makes t hold harder to meet. If t hold is not met (race conditions), the circuit malfunctions independent of the clock period! T T +   > 0  + t hold T +   t c-q + t plogic + t su so T  t c-q + t plogic + t su -  t hold +  ≤ t cdlogic + t cdreg so t hold ≤ t cdlogic + t cdreg -  1234  Clock and data flow in the same direction T : t hold :

8. CSE477 L19 Timing Issues; Datapaths.8Irwin&Vijay, PSU, 2003 Negative Clock Skew DQ R1 Combinational logic DQ R2 clk In t clk1 t clk2 delay  Clock and data flow in opposite directions T T +   < 0 1234 T : t hold :

9. CSE477 L19 Timing Issues; Datapaths.9Irwin&Vijay, PSU, 2003 Negative Clock Skew DQ R1 Combinational logic DQ R2 clk In t clk1 t clk2 delay  Clock and data flow in opposite directions T T +   < 0 T +   t c-q + t plogic + t su so T  t c-q + t plogic + t su -  t hold +  ≤ t cdlogic + t cdreg so t hold ≤ t cdlogic + t cdreg -  1234   < 0: Degrades performance, but t hold is easier to meet (eliminating race conditions) T : t hold :

10. CSE477 L19 Timing Issues; Datapaths.10Irwin&Vijay, PSU, 2003 Clock Jitter  Jitter causes T to vary on a cycle-by- cycle basis R1 Combinational logic clk In t clk T -t jitter +t jitter T :

11. CSE477 L19 Timing Issues; Datapaths.11Irwin&Vijay, PSU, 2003 Clock Jitter  Jitter causes T to vary on a cycle-by- cycle basis R1 Combinational logic clk In t clk T -t jitter +t jitter T - 2t jitter  t c-q + t plogic + t su so T  t c-q + t plogic + t su + 2t jitter  Jitter directly reduces the performance of a sequential circuit T :

12. CSE477 L19 Timing Issues; Datapaths.12Irwin&Vijay, PSU, 2003 Combined Impact of Skew and Jitter DQ R1 Combinational logic DQ R2 In t clk1 t clk2  Constraints on the minimum clock period (  > 0)   > 0 with jitter: Degrades performance, and makes t hold even harder to meet. (The acceptable skew is reduced by jitter.) T T +   > 0 1612 -t jitter T  t c-q + t plogic + t su -  + 2t jitter t hold ≤ t cdlogic + t cdreg –  – 2t jitter

13. CSE477 L19 Timing Issues; Datapaths.13Irwin&Vijay, PSU, 2003 Clock Distribution Networks  Clock skew and jitter can ultimately limit the performance of a digital system, so designing a clock network that minimizes both is important l In many high-speed processors, a majority of the dynamic power is dissipated in the clock network. l To reduce dynamic power, the clock network must support clock gating (shutting down (disabling the clock) units)  Clock distribution techniques l Balanced paths (H-tree network, matched RC trees) -In the ideal case, can eliminate skew -Could take multiple cycles for the clock signal to propagate to the leaves of the tree l Clock grids -Typically used in the final stage of the clock distribution network -Minimizes absolute delay (not relative delay)

14. CSE477 L19 Timing Issues; Datapaths.14Irwin&Vijay, PSU, 2003 H-Tree Clock Network Clock Idle condition Gated clock Can insert clock gating at multiple levels in clock tree Can shut off entire subtree if all gating conditions are satisfied  If the paths are perfectly balanced, clock skew is zero

15. CSE477 L19 Timing Issues; Datapaths.15Irwin&Vijay, PSU, 2003 Clock Grid Network  Distributed buffering reduces absolute delay and makes clock gating easier, but is sensitive to variations in the buffer delay Clock secondary clock buffers local logic area main clock buffer  The secondary buffers isolate the local clock nets from the upstream load and amplify the clock signals degraded by the RC network l decreases absolute skew l gives steeper clocks  Only have to bound the skew within the local logic area

16. CSE477 L19 Timing Issues; Datapaths.16Irwin&Vijay, PSU, 2003 DEC Alpha 21164 (EV5) Example  300 MHz clock (9.3 million transistors on a 16.5x18.1 mm die in 0.5 micron CMOS technology) l single phase clock  3.75 nF total clock load l Extensive use of dynamic logic  20 W (out of 50) in clock distribution network  Two level clock distribution l Single 6 inverter stage main clock buffer at the center of the chip l Secondary clock buffers drive the left and right sides of the clock grid in m3 and m4  Total equivalent driver size of 58 cm !!

17. CSE477 L19 Timing Issues; Datapaths.17Irwin&Vijay, PSU, 2003 Secondary Clock Buffers

18. CSE477 L19 Timing Issues; Datapaths.18Irwin&Vijay, PSU, 2003 Clock Skew in Alpha Processor  Absolute skew smaller than 90 ps  The critical instruction and execution units all see the clock within 65 ps

19. CSE477 L19 Timing Issues; Datapaths.19Irwin&Vijay, PSU, 2003 Dealing with Clock Skew and Jitter  To minimize skew, balance clock paths using H-tree or matched-tree clock distribution structures.  If possible, route data and clock in opposite directions; eliminates races at the cost of performance.  The use of gated clocks to help with dynamic power consumption make jitter worse.  Shield clock wires (route power lines – V DD or GND – next to clock lines) to minimize/eliminate coupling with neighboring signal nets.  Use dummy fills to reduce skew by reducing variations in interconnect capacitances due to interlayer dielectric thickness variations.  Beware of temperature and supply rail variations and their effects on skew and jitter. Power supply noise fundamentally limits the performance of clock networks.

20. CSE477 L19 Timing Issues; Datapaths.20Irwin&Vijay, PSU, 2003 Major Components of a Computer Processor Control Datapath Memory Devices Input Output  Modern processor architecture styles (CSE 431) l Pipelined, single issue (e.g., ARM) l Pipelined, hardware controlled multiple issue – superscalar l Pipelined, software controlled multiple issue – VLIW l Pipelined, multiple issue from multiple process threads - multithreaded

21. CSE477 L19 Timing Issues; Datapaths.21Irwin&Vijay, PSU, 2003 Basic Building Blocks  Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers, decoders  Control l Finite state machines (PLA, ROM, random logic)  Interconnect l Switches, arbiters, buses  Memory l Caches, TLBs, DRAM, buffers

22. CSE477 L19 Timing Issues; Datapaths.22Irwin&Vijay, PSU, 2003 MIPS 5-Stage Pipelined (Single Issue) Datapath pipeline stage isolation register FetchDecodeExecuteMemoryWriteBack clk Icache precharge Dcache precharge RegWrite

23. CSE477 L19 Timing Issues; Datapaths.23Irwin&Vijay, PSU, 2003 Datapath Bit-Sliced Organization Control Flow Bit 0 Bit 1 Bit 2 Bit 3 Tile identical bit-slice elements Register File Pipeline RegisterAdderShifterPipeline RegisterMultiplexer Data Flow Pipeline Register From I$ Pipeline Register To/From D$

24. CSE477 L19 Timing Issues; Datapaths.24Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l Adder design -Reading assignment – Rabaey, et al, 11.3  Reminders l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th ) l Project final reports due December 4 th l Final grading negotiations/correction (except for the final exam) must be concluded by December 10 th l Final exam scheduled -Tuesday, December 16 th from 10:10 to noon in 118 and 113 Thomas