1. Clockless Chips Under the esteemed guidance of Romy Sinha Lecturer, REC Bhalki Presented by: Lokesh S. Woldoddy 3RB05CS122 Date:11 April 2009.

2. Presentation on Clockless Chips2 Content: Introduction. Concept of clock. Working of synchronous circuit. Asynchronous logic circuits. GENERAL MODEL OF ASYNCHRONOUS DESIGN Synchronous and asynchronous. How do they work? Clock time cycle vs. clockless time cycle. Simple and efficient design DIFFERENT STYLES. Problems with Synchronous Approach. Synchronous circuit. Some features. Challenges. Advantages. Applications. Conclusion. References.

3. Presentation on Clockless Chips3 Introduction. Struggle for the improvement in the microprocessor’s performance/functioning. –Pipelining –(Simultaneous) Multi-threading –Clockless / Asynchronous logic } Synchronous

4. Presentation on Clockless Chips4 Concept of clock CLOCK: –Tiny crystal oscillator. –Sets basic rhythm used throughout the machine. ADVANTAGES: – S ignals the device of the chip when to i/p or o/p. –This functionality makes designing of synchronous chip easier. 4

5. Presentation on Clockless Chips5 Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html 5

6. Presentation on Clockless Chips6 Clockless chips (Asynchronous logic circuits) Colckless chips/Asynchronous/self-timed circuits. Functions away from the clock. Different parts work at different speeds. Hand-off the result immediately.

7. Presentation on Clockless Chips7 GENERAL MODEL OF ASYNCHRONOUS DESIGN: Adapted:David Geer,”Is it time for clockless chips?,”IEEE paper,pp.18-21,March 2005 7

8. Presentation on Clockless Chips8 Courtesy: Computers without clocks – Ivan E Sutherland and Jo Ebergen

9. Presentation on Clockless Chips9 How do they work? No pure asynchronous chips are available. Uses handshake signals for the data exchange. Data moves only when required, not always. –Minimizes power consumption. –Less EMI  less noise  more applications. –Stream data applications.

10. Presentation on Clockless Chips10 Clock time cycle vs. clockless time cycle Courtesy: Fulcrum Microsystems.

11. Presentation on Clockless Chips11 Simple and efficient design No centralized clock required. Standardized components can be used.

12. Presentation on Clockless Chips12 DIFFERENT STYLES: Simplest implementation of asynchronous design. Assumption: we know the largest amount of time for each component to perform its task. Very similar to synchronous design. Prototype delay is introduced here. 12

13. Presentation on Clockless Chips13 Problems with Synchronous Approach Distributing the clock globally. Wastage of energy. Traverse the chip’s longest wires in one clock cycle. Order of arrival of the signals is unimportant. Clocks themselves consume lot of energy ( ~30% ).

14. Presentation on Clockless Chips14 Synchronous circuit Longest path determines the minimum clock period. Dissipation of energy for each clock cycle. EMI is more in synchronous elements.

15. Presentation on Clockless Chips15 Some features Integrated pipelining mode. –Domino logic. –Delay – insensitive. Two different implementation details –Dual rail. –Bundled data.

16. Presentation on Clockless Chips16 Challenges Interfacing between synchronous and asynchronous –Many devices available now are synchronous in nature. –Special circuits are needed to align them. Lack of expertise. Lack of tools. Engineers are not trained in these fields. Academically, no courses available.

17. Presentation on Clockless Chips17 Advantages (technical look) Asynchronous for higher performance: –Data-dependent delays. –All carry bits need to be computed.

18. Presentation on Clockless Chips18 Advantages Works at its average speed. Low power consumption.  Twice life-time. Less heat generated.  Good to mobile devices. Less EMI  less noise  more applications. Smart cards (due to asynchronous nature).

19. Presentation on Clockless Chips19 Applications:  In the lab.  In mobile electronics.  In personal computers.  In encryption devices. 19

20. Presentation on Clockless Chips20 Conclusion: Clocks are getting faster, while chips are getting bigger both of which make clock distribution harder o There are also various other problems associated with it. So we could only get out of it, if more focus, especially at the university level is given to the asynchronous design. o It is certainly a challenge, but as software community is moving towards concurrency, hardware community must move to incorporate asynchronous logic.

21. Presentation on Clockless Chips21 References Scanning the Technology: Applications of Asynchronous Circuits – C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick Computers without clocks – Ivan E Sutherland and Jo Ebergen. http://ieeexplore.ieee.org/iel5/2/30617/01413111.pdf (October 2001) http://ieeexplore.ieee.org/iel5/2/30617/01413111.pdf http://csdl2.computer.org/comp/mags/dt/2003/06/d6005.pdf http://www1.cs.columbia.edu/async/misc/technologyreview_oct_0 1_2001.html http://www1.cs.columbia.edu/async/misc/technologyreview_oct_0 1_2001.html http://www.technologyreview.com/articles/01/10/tristram1001.asp http://www1.cs.columbia.edu/async/misc/economist/Economist_c om.htm http://www1.cs.columbia.edu/async/misc/economist/Economist_c om.htm

22. Presentation on Clockless Chips22 Thank you