1. INSIDE – Update meeting PET DAQ 24 March 2014

2. Refresh from the last meetings Objectives of the PET DAQ – Provide a full in-beam (full-beam) PET system able to sustain annihilation and prompt photon rates during the beam irradiation – Instant single rates in the microsecond range are currently unknown – As a first guess we take 30 kHZ/cm 2 as the desired maximum sustainable single rate ( ∼ 6× with respect to DoPET) – Provide a dedicated PET scanner with a coincidence window (CW) of 500 ps

3. Data acquisition flow Each SiPM/ASIC pair can handle single rates at 180 kHZ The 5 cm x 5 cm module will acquire at 720 kHZ Data collected by two FPGAs – TX, coupled to the ASIC – RX, plugged on the mainboard Data packet is 10 B The expected module output bandwidth is 7.2 MB/s

4. Updates

6. Motherboard HW development Functional design ✔ Schematic design ✔ Mechanical design ✔ PCB design (in progress) Construction and assembly ✖ Initial delivery 12/2013, expected delivery 4/2013

7. Motherboard FW development Functional architecture design ✔ USB interface (imported from DoPET) RX interface (under development) Coincidence sorter and processor ✖ Expected first version delivery 12/2014 (depending on HW status)

8. Motherboard SW development Largely imported from DoPET Server/client architecture, suitable for multi- modal integration (same as for IrisPET) No specific developments are being made at the moment

9. RX board development Initial FW development with the SoCKit board Cyclone V SX 5CSXFC6D6 FPGA Equipped with ARM processor

10. RX board development Customizing and producing a new board based on the same technology The HSMC connector is kept to communicate with the TX board + Motherboard connector + Motherboard connector

11. RX FW board development The RX FW architecture is relatively simple – SPI slave component – FIFO buffers – SERDES

12. RX SW board development The RX does not require SW development However, the ARM processors offer simple and flexible solutions to processing problems This is a new aspect of SoC FPGA that is under investigation