1. ECE 699: Lecture 2
Introduction to Zynq

2. Required Reading The ZYNQ Book Chapter 1: Introduction
Chapter 2: The Zynq Device (“What is it?)
Chapter 5: Applications and Opportunities
(“What can I do with it?”)
Xilinx Educational Video
Why Zynq?

3. What is Software/Hardware Codesign?
Integrated design of systems that consist
of hardware and software components
Analysis of HW/SW boundaries and interfaces
Evaluation of design alternatives

4. General-Purpose Computing
Embedded Systems vs.
General-Purpose Computing
Source: ETHZ, Prof. Lothar Thiele

5. Idea of an Embedded System
Source: ETHZ, Prof. Lothar Thiele

6. Software vs. Hardware Trade-offs
Source: A Practical Introduction to Hardware/Software Codesign

7. Energy Efficiency of AES Implementations
on Various Platforms
Source: A Practical Introduction to Hardware/Software Codesign

8. Hardware and Software Design
Distinct Features of
Hardware and Software Design
Hardware
Software
Design Paradigm
Decomposition in space
Decomposition in time
Resource
Area (#gates, #Slices)
Time (#Cycles)
Flexibility
Must be designed in
Implicit
Parallelism
Modeling
Model ≠ Implementation
Model ≈ Implementation
Reuse
Uncommon
Common

9. Why Codesign?

10. System Design Flow
Software
Hardware
Source: ETHZ, Prof. Lothar Thiele

11. Implementation Alternatives
Source: ETHZ, Prof. Lothar Thiele

12. Traditional Discrete Component Architecture
Source: The Zynq Book

13. System-on-a-Board
Source: The Zynq Book

14. System-on-Chip (SoC)
Source: The Zynq Book

15. FPGA with Soft Processor Core
Source: The Zynq Book

16. A Simplified Model of the Zynq Architecture
Source: The Zynq Book

17. Simplified Hardware Architecture
of an Embedded SoC
Source: The Zynq Book

18. Mapping of an Embedded SoC Hardware Architecture to Zynq
Source: The Zynq Book

19. Mapping of an Embedded SoC Hardware Architecture to Zynq
Source: Xilinx White Paper: Extensible Processing Platform

20. Comparison with Alternative Solutions
ASIC
ASSP
2 Chip Solution
Zynq
Performance ✚ 
Power −
Unit Cost
Total Cost of Ownership
Risk
Time to Market
Flexibility
Scalability
positive, − negative,  neutral
Source: Xilinx Video Tutorials

21. Application Specific Standard Product
an integrated circuit that implements a specific function that appeals to a wide market
off-the-shelf
listed in catalogs
used in all industries, from automotive to communications
Example: video and/or audio encoding and/or decoding

22. Zynq Highlights
Source: Xilinx Video Tutorials

23. ARM Processor Roadmap
Source: Xilinx White Paper: Extensible Processing Platform

24. Basic Design Flow for Zynq SoC
Source: The Zynq Book

25. Design Flow for Zynq SoC
Source: Xilinx White Paper: Extensible Processing Platform

26. Zynq SoC Ecosystem

27. Zynq SoC Ecosystem
Source: The Zynq Book

28. Alternative Solutions
Xilinx Zynq
Zynq-7000 All Programmable
SoCs with Cortex-A9 MPCore
Altera Arria V & Cyclone V
Hard processor system (HPS)
with Cortex-A9 MPCore
Microsemi Smartfusion2
Cortex M3

29. The Zynq Processing System
Source: The Zynq Book

30. Simplified Block Diagram of the Application Processing Unit (APU)
Source: The Zynq Book

31. SIMD (Single Instruction Multiple Data) Media Processing Engine (MPE)
Processing in the NEON
Media Processing Engine (MPE)
Source: The Zynq Book

32. Programmable Logic (PL)
CLBs and IOBs
Source: The Zynq Book

33. Programmable Logic (PL)
BRAMs and DSP units
Source: The Zynq Book

34. SoC Buses
Source: M.S. Sadri, Zynq Training

35. Solution Adopted in ZYNQ
Advanced Microcontroller Bus Architecture (AMBA):
an open-standard, on-chip interconnect specification
for the connection and management of functional
blocks in system-on-a-chip (SoC) designs.
First version introduced by ARM in 1996.
AMBA Advanced eXtensible Interface 4 (AXI4):
the fourth generation of AMBA interface defined
in the AMBA 4 specification, targeted at
high performance, high clock frequency systems.
Introduced by ARM in 2010.
Source: M.S. Sadri, Zynq Training

36. Basic Concepts
Source: M.S. Sadri, Zynq Training

37. Information Exchanged Between AXI Master and AXI Slave
Source: M.S. Sadri, Zynq Training

38. AXI Interconnects and Interfaces
ACP - Accelerator Coherency Port
SCU - Snoop Control Unit
Source: The Zynq Book

39. General-Purpose Port Summary
GP ports are designed for maximum flexibility
Allow register access from PS to PL or PL to PS
Good for Synchronization
Prefer ACP or HP port for data transport

40. High-Performance Port Summary
HP ports are designed for maximum bandwidth access to external memory and OCM
When combined can saturate external memory and OCM bandwidth
– HP Ports : 4 * 64 bits * 150 MHz * 2 = 9.6 GByte/sec
– external DDR: 1 * 32 bits * 1066 MHz * 2 = 4.3 GByte/sec
– OCM : 64 bits * 222 MHz * 2 = 3.5 GByte/sec
Optimized for large burst lengths and many outstanding transactions
Large data buffers to amortize access latency
Efficient upsizing/downsizing for 32 bit accesses

41. Accelerator Coherency Port (ACP) Summary
ACP allows limited support for Hardware Coherency
– Allows a PL accelerator to access cache of the Cortex-A9 processors
– PL has access through the same path as CPUs including caches, OCM, DDR, and peripherals
– Access is low latency (assuming data is in processor cache) no switches in path
ACP does not allow full coherency
– PL is not notified of changes in processor caches
– Use write to PL register for synchronization
ACP is compromise between bandwidth and latency
– Optimized for cache line length transfers
– Low latency for L1/L2 hits
– Minimal buffering to hide external memory latency
– One shared 64 bit interface, limit of 8 masters

42. The Zynq Processing System
Source: The Zynq Book

43. Using Extended Multiplexed Input/Output
(EMIO) to Interface Between PS and PL
Source: The Zynq Book

44. Automotive Applications

45. Automotive Applications Lane and Road Sign Recognition
Source: The Zynq Book

46. Detection of Cars at a Junction
Computer Vision
Detection of Cars at a Junction
Source: The Zynq Book

47. Smart
Home
Source: The Zynq Book

48. Software Defined Radio (SDR)
a radio which can be reconfigured while in operation
all of the physical layer functions are software defined
used initially in military applications (Joint Tactical Radio Systems – JTRS, 1998), recently entering the commercial arena
can support multiple radio standards (for cellular networks [2G, 3G, 4G], WiFi, Bluetooth, GPS reception, etc.)
may be used in smartphones, tablets, e-readers, TVs, cars, transportation, emergency services, etc.)

49. Software Defined Radio (SDR)
NCO – numerically
controlled oscillator
IF – intermediate frequency;
an incoming signal is shifted
to an IF for amplification
before final detection
Source: The Zynq Book

50. Software Defined Radio (SDR)
The Physical Layer (PHY) – the part of radio directly adjacent to the Radio Frequency (RF) circuitry and air interface
Computationally intensive, implementing high-speed filters, modulation, coding, DSP algorithms, support for ADC and DAC
Most complex computations implemented in hardware (with parameters set from software)
Less complex computations can be performed in either hardware or software

51. Cognitive Radio
an intelligent radio that can be programmed and configured dynamically
its transceiver is designed to use the best (under-used) wireless channels in its vicinity
automatically detects available channels in wireless spectrum, and changes its transmission or reception parameters accordingly
allows more concurrent wireless communications in a given spectrum band at one location
a form of dynamic spectrum management

52. Communication Systems
Wireless
Basestation
Satellite
Groundstation
Wired Network
Switches
Source: The Zynq Book

53. Control and Instrumentation Systems
Industrial
Control
Room
Wind
Turbines
High Energy
Physics
Experiment
Source: The Zynq Book

54. Robot Assisted Surgery
Medical Applications
MRI Scanning
Robot Assisted Surgery
Source: The Zynq Book

55. Implementation Platforms
Choice Among Various
Implementation Platforms
Differentiation is concerned with how a firm distinguishes its offering from
those of its competitors
Source: Xcell Journal, no. 88, Q3 2014

56. Advantages of Zynq
Source: Xcell Journal, no. 88, Q3 2014

57. Comparison of the Development
Time & Cost
Source: Xcell Journal, no. 88, Q3 2014

58. Academic Subjects to which Zynq is Relevant
Source: The Zynq Book

59. The ZYBO Development Board
Source: The Zynq Book

60. ZYBO Board
Source: ZYBO Reference Manual

61. ZYBO Board Components
Source: ZYBO Reference Manual

62. ZYBO General Purpose Input Output (GPIO)
Source: ZYBO Reference Manual

63. VGA
Circuit
Source: ZYBO Reference Manual

64. VGA Connector
Source: ZYBO Reference Manual

65. USB-UART Bridge
Source: ZYBO Reference Manual

66. MicroSD Slot
Source: ZYBO Reference Manual

67. Ethernet Connector
Source: ZYBO Reference Manual

68. Pmod Connector
Source: ZYBO Reference Manual