1. Introduction to Exceptions 1 Introduction to Exceptions ARM Advanced RISC Machines

2. Introduction to Exceptions 2 Interrupts or Exceptions *Naming conventions vary a lot. *IBM and Intel call them Interrupts *Motorola calls them Exceptions *Sometimes also called Traps *Often the terms are used interchangeably

3. Introduction to Exceptions 3 Programmed Input/Output *Controlling or accessing an external device can tie-up the processor. *With “Programmed I/O” the CPU repeatedly reviews the device status. e.g. start the device, and poll for completion processor 100% tied up, waiting for device ready. Program initiated Start Device Poll status Wait until device ready CPU Device Code

4. Introduction to Exceptions 4 Exception Input / Output Program initiated Start Device Interrupt Interrupt Service Routine Return *Interrupts or exceptions are events that change the program flow *Hardware interrupts only concern the processor when necessary.

5. Introduction to Exceptions 5 Exception Class (1) *Synchronous or asynchronous Synchronous occurs in the same place in the program every time Asynchronous can occur anywhere *User Requested or Coerced An interrupt caused by the program flow Interrupt caused by external event not under control of the program

6. Introduction to Exceptions 6 Exception Class (2) *Between or within instructions Does the event prevent the execution of the instruction Will it be recognised between instructions? *Resume or Terminate If the event ceases execution of the program it is classed as terminate *Maskable or Non-Maskable If the interrupt can be prevented from affecting program flow by the user then it is classed as maskable.

7. Introduction to Exceptions 7 Exception Types *Some examples of events which will cause exceptions I/O Device Request –Eg: Ethernet controller requires attention Operating System Service –Task can only be executed in a priveliged mode Page Fault –Program or data not in memory Integer arithmetic overflow Power failure

8. Introduction to Exceptions 8 Exception Classification *The exceptions could be classified according to the class I/O Request –Asynchronous, Coerced, Nonmaskable, Between, Resume Operating System Service –Synchronous, User Request, Nonmaskable, Between, Resume Page Fault –Synchronous, Coerced, Nonmaskable, Within, Resume Integer Arithmetic Overflow –Synchronous, Coerced, Maskable, Within, Terminate Power Failure –Asynchronous, Coerced, Nonmaskable, Within, Terminate

9. Introduction to Exceptions 9 Exception Response *Two basic methods *Force PC to an exception vector Interrupt vector contains an instruction to branch to the Interrupt Service Routine ISR must then poll for the cause of the interrupt *External Hardware provides address Jump directly to the correct ISR No polling required therefore faster

10. Introduction to Exceptions 10 Exception Flow *Interrupt Flow from taking interrupt to re-starting program. Reset Undefined Inst FIQ IRQ Reserved Data Abort Prefetch Abort Software Interrupt ARM Program Interrupt Service Routine Branch PC loaded with Interrupt Vector Back to executing from next instrcution after interrupt ocurred Restore PC and Processor State

11. Introduction to Exceptions 11 Basic ISR Sequence *The basic sequence of handling an exception Save program counter Save processor registers Disable Exceptions –Those that can be masked or lower priority Clear the source of the Exception Execute the Handler Program ( Eg: read serial port ) Enable Exceptions Restore processor registers Restore program counter Continue execution

12. Introduction to Exceptions 12 ARM Specific Features *ARM has features aimed at speeding up exception handling Automatic saving of the program counter and current program status register No need to save all registers to memory –Some are saved automatically within the processor Fast instructions for loading and storing to/from memory *No “return from interrupt” instruction Other processors have RETI instruction ARM does not, ARM relies on the programmer to handle this. Eg: using a MOV instruction

13. Introduction to Exceptions 13 Exception Priority *Some events are more important than others Eg: Power failure *Exceptions need to be prioritised *ARM has fixed priority for Exceptions (1) Reset ( Highest priority ) (2) Data Abort (3) FIQ - fast interrupt (4) IRQ - normal interrupt (5) Prefetch Abort (6) Undefined Instruction, Software Interrupt ( Lowest Priority )

14. Introduction to Exceptions 14 Exception Control *An exception mechanism requires: a “MASK” flag to enable/disable the recognition of the request a mechanism for synchronising asynchronousor clock and instruction flow a defined protocol for clearing the source of interrupts CPSR Condition Code Flags Mode N ZCV 28 318 40 I F I = 1, disables the IRQ. F = 1, disables the FIQ. Interrupt Disable bits. Mode Bits M[4:0] define the processor mode. Six modes are valid.

15. Introduction to Exceptions 15 Interrupt reentrancy *Interrupts (e.g. FIQs) are normally handled serially as the mask flag is disabled during the interrupt service routine. *However, if the service routine clears the mask bit: other similar priority interrupts will be serviced before the current interrupt is processed the service routine is said to be reentrant Process Interrupt Service Routine Return Interrupt Service Routine Return

16. Introduction to Exceptions 16 Interrupt Latency External Interrupts are not recognised immediately. Clock cycles are required for synchronisation and recognition of the interrupt. Multiple cycle instructions prevent the interrupt from being recognised. –Eg: Multiply instruction on ARM MCLK Interrupt Latency FIQ (or IRQ)

17. Introduction to Exceptions 17 Interrupt latency - continued *A synchronised (and enabled) interrupt will generate an interrupt at the end of the current instruction. *The worst case instruction is a Load Multiple (LDM): –of sixteen registers –which changes the PC –and causes a Data Abort this LDM takes 20 cycles. *The data Abort handler must be entered (3 cycles) before the FIQ is entered *Entering the abort and interrupt vectors adds an overhead of two clock cycles to fill the pipeline. *Thus the worst case latency for FIQ is = Tsync + Tldm + Tdabt + Tfiq = 3 + 20 + 3 + 2 = 28 cycles or 1.4usec at 20MHz. *IRQ has a latency extended by the longest FIQ service routine.