1. Ch 5. ARM Instruction Set  Data Type: ARM processors supports six data types  8-bit signed and unsigned bytes  16-bit signed and unsigned half-words  32-bit signed and unsigned words  ARM instructions are all 32-bit words and Thumb instructions are half-words  Internally, all ARM operations are on 32-bit operands 1

2. Privileged Modes  ARM has privileged operating modes  To handle exceptions and supervisor calls  Defined by the bottom five bits of the CPSR  SPSR  Each privileged mode (except system mode) has associated with it a Saved Program Status Register  This register is used to save the state of the CPSR 2

3. Exceptions  ARM exceptions may be considered in three groups  Exception generated as the direct effect of executing an instruction  Software interrupts, undefined instructions and prefetch aborts  Exceptions generated as a side-effect of an instruction  Data aborts  Exceptions generated externally, unrelated to the instruction flow 3

4. Exception Entry  The processor performs the following sequence of actions:  It changes to the operating mode corresponding to the particular exception  It saves the address of the instruction following the exception entry instruction in r14 of the new mode  It saves the old value of the CPSR in the SPSR of the new mode  It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fast interrupt, disables further fast interrupts by setting bit 6 of the CPSR  It forces the PC to begin executing at the relevant vector address given in Table 5.2 4

5. Table 5.1 Normally the vector address will contain a branch to the relevant routine The two banked registers in each of the privileged modes are used to hold the return address and a stack pointer 5

6. Exception Return  Any modified user registers must be restored from the handler’s stack  The CPSR must be restored from the appropriate SPSR  The PC must be changed back to the relevant instruction address in the user instruction stream 6

7. Conditional Execution  Every instruction is conditionally executed  Each of the 16 values of the condition field causes the instruction to be executed or skipped according to the values of the N, Z, C, and V flags in the CPSR 7

8. ARM Condition Codes 8

9. Branch and Branch with Link (B, BL) 9  Branch and Branch with Link instructions are the standard way to cause a switch in the sequence of instruction execution  Binary Encoding  Description  Shift the 24-bit offset left two places and add it to PC+8  The range of the branch instructions : +/- 32 Mbytes  The Branch with Link  ‘L’ bit set: moves the address of the instruction following the branch into the link register (r14)

10. Assembly Format and Example 10  Assembler Format  B{L}{ }  Examples  To execute a loop ten times:  To call a subroutine: MOV r0, #10 LOOP.. SUBSr0, #1 BNELOOP MOV r0, #10 LOOP.. SUBSr0, #1 BNELOOP BLSUB.. SUB.. MOVPC, r14 BLSUB.. SUB.. MOVPC, r14

11. 5.5: Branch, Branch with Link and eXchange (BX, BLX) 11  Available on ARM chips which support the Thumb  BLX is available only on ARM processors that support v5T  Binary Encoding condRm 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 31282765430 1L 1 1 1 0 1H 24-bit signed word offset 3128272524230 (1) BX|BLX Rm (2) BLX label

12. Description 12  The first format  Rm[0] copied to T bit in CPSR, Rm[31:1] into the PC  If Rm[0] is 1, switches to Thumb state, executing at the address in Rm aligned to a half-word boundary by clearing the bottom bit  If Rm[0] is 0, switches to ARM state, executing at the address in Rm aligned to a word boundary by clearing Rm[1]  The second format  Sign extending the 24-bit offset  Shifting it left two places  Adding it to the PC which contains the address of the BX instruction plus 8  ‘H’ bit added into bit 1 of the resulting address, allowing an odd half-word address (Thumb state)

13. Assembler Format and Example 13  Assembler Format  1: B{L}X{ }Rm  2: BLX  Examples CODE32; ARM code follows.. BLXTSUB; call Thumb subroutine.. CODE16; Start of Thumb code TSUB.. BXr14; return to ARM code

14. 5.6: Software Interrupt (SWI) - 1 14  The SWI is used to for calls to the operating system and is often called a ‘supervisor call’  It puts the processor into supervisor mode and begins executing instructions from address 0x08  Binary Encoding  Description  Save the address of the next instruction in r14_svc  Save the CPSR in SPSR_svc  Enter supervisor mode and disable IRQ (but not FIQ) by setting CPSR[4:0] to 10011 2 and CPSR[7] to 1  Set the PC to 08 16 and begin executing the instruction here

15. Assembler Format and Example 15  Assembler Format  SWI{ }  Examples MOVr0, #’A’; get ‘A’ into r0 SWISWI_WriteC

16. 5.7: Data Processing Instructions 16  Binary Encoding

17. Description  3-address format  The two source operands and the destination register are specified independently  One source operand is always a register  The second may be a register, a shifted register or an immediate value  When the instruction does not require all the available operands the unused register field should be set to zero 17

18. ARM Data Processing Instructions 18

19. Condition Codes  These instructions allow direct control of whether or not the processor’s condition codes are affected by their execution through the S bit (bit 20)  The N flag is set if the results is negative  The Z flag is set if the result is zero  The C flag is set to the carry-out from the ALU when the operation is arithmetic or to the carry-out from the shifter otherwise  The V flag is set in and arithmetic operation if there is an overflow from bit 30 to bit 31 19

20. Operations ADD r0, r1, r2r0 := r1 + r2 ADC r0, r1, r2r0 := r1 + r2 + C SUB r0, r1, r2r0 := r1 - r2 SBC r0, r1, r2r0 := r1 - r2 + C - 1 RSB r0, r1, r2r0 := r2 – r1 RSC r0, r1, r2r0 := r2 – r1 + C - 1 Arithmetic Operations Bit-wise Logical Operations AND r0, r1, r2r0 := r1 and r2 ORR r0, r1, r2r0 := r1 or r2 EOR r0, r1, r2r0 := r1 xor r2 BIC r0, r1, r2r0 := r1 and (not) r2 Register Movement MOV r0, r2r0 := r2 MVN r0, r2r0 := not r2 Comparison Operations CMP r1, r2set cc on r1 - r2 CMN r1, r2set cc on r1 + r2 TST r1, r2set cc on r1 and r2 TEQ r1, r2set cc on r1 xor r2 20

21. 5.8: Multiply Instructions 21  ARM multiply instructions produce the product of two 32-bit binary numbers held in registers  Binary Encoding

22. Description  ‘RdHi:RdLo’ is the 64-bit number formed by concatenating RdHi (the most significant 32 bits) and RdLo (the least significant 32 bits). ‘[31:0]’ selects only the least significant 32 bits of the result  Simple assignment is denoted by ‘:=’.  Accumulation (adding the right-hand side to the left) is denoted by ‘+=’. 22

23. Assembler Formats and Examples 23  Assembler Format  MUL{ }{S}Rd, Rm, Rs  MLA{ }{S}Rd, Rm, Rs, Rn  { }{S}RdHi, RdLo, Rm, Rs  is (UMULL, UMLAL, SMULL, SMLAL)  Examples MOVr11, #20; initialize loop counter MOVr10, #0; initialize total LOOPLDRr0, [r8], #4; get first component LDRr1, [r9], #4;.. And second MLAr10, r0, r1, r10; accumulate product SUBSr11, r11, #1; decrement loop counter BNELOOP

24. 5.9: Count Leading Zeros (CLZ-architecture v5T only) 24  Binary Encoding  Assembler format  CLZ{ }Rd, Rm  Example  MOVr0, #&100  CLZr1, r0; r1 := 23

25. 5. 10: Single Word and Unsigned Byte Data Transfer Instructions 25  Binary Encoding

26. Assembler Format and Examples 26  Assembler format  LDR|STR{ }{B}Rd, [Rn, ]{!} ; pre-indexed  LDR|STR{ }{B}{T}Rd, [Rn], ; post-indexed  LDR|STR{ }{B}Rd, LABEL ; PC-relative  Examples LDRr1, UARTADD; UART address into r1 STRBr0, [r1]; store data to UART … UARTADD &&1000000; address literal

27. Half-Word and Signed Byte Data Transfer Instructions 27  Binary Encoding

28. Assembler Formats 28  Assembler format  LDR|STR{ }H|SH|SBRd, [Rn, ]{!} ; pre-indexed  LDR|STR{ } H|SH|SB Rd, [Rn], ; post-indexed  Example ADRr1, ARRAY1; half-word array start ADRr2, ARRAY2; word array start ADRr3, ENDARR1; ARRAY1 end + 2 LOOPLDRSHr0, [r1], #2; get signed half-word STRr0, [r2], #4; save word CMPr1, r3; check for end of array BLTLOOP; if not finished, loop

29. Multiple Register Transfer Instructions 29  Binary Encoding  Assembler format  LDM|STM{ } Rn{!},

30. Swap Memory and Register Instructions (SWP) 30  Binary encoding  Assembler format  SWP{ }{B}Rd, Rm, [Rn]  Example ADRr0, SEMAPHORE SWPBr1, r1, [r0]; exchange byte

31. Status Register to General Register Transfer Instructions 31  Binary encoding  Assembler format  MRS{ }Rd, CPSR|SPSR  Example MRSr0, CPSR; move the CPSR to r0 MRSr3, SPSR; move the SPSR to r3

32. General Register to Status Register Transfer Instructions 32  Binary encoding cond0 operand #field1 1 3128272625242322212019161512110 field mask 8-bit immediate1 2511870 Rm 11430 0 25 0 0 0 0 operand register 1 0R SPSR/CPSR #rot immediate alignment

33. Assembler Formats 33  Assembler format  MSR{ }CPSR_f|SPSR_f, #  MSR{ }CPSR_ |SPSR_, Rm  Field  c – control – PSR[7:0], x –extension – PSR[15:8]  s – status – PSR[23:16],  f – flags – PSR[31:24]

34. Examples 34  Examples  To set the N, Z, C, and V flags  MSRCPSR_f, #&f0000000 ; set all the flags  To set just the C flag, preserving N, Z, and V  MRSr0, CPSR; move the CPSR to r0  ORRr0, r0, #&20000000; set bit 29 of r0  MSRCPSR_f, r0; move back to CPSR  To switch from supervisor mode into IRQ mode  MRSr0, CPSR; move the CPSR to r0  BICr0, r0, #&1f; clear the bottom 5 bits  ORRr0, r0, #&12; set the bits to IRQ mode  MSRCPSR_c, r0; move back to CPSR

35. 5.16: Coprocessor Instructions 35  Coprocessor  The ARM architecture supports a general mechanism for extending the instruction set through the addition of coprocessors  General mechanism to extend the instruction set through the addition to the core  Example : system controller such as MMU & cache. FPU  Coprocessor registers  Private to coprocessor  The ARM has sole responsibility for control flow  Coprocessor concerns only the data processing and data transfer operations

36. Coprocessor Data Operations 36  Coprocessor data operations (CDP)  These instructions are used to control internal operations on data in coprocessor registers  Binary encoding  Assembler format  CDP { },, CRd, CRn, CRm{, }  Examples  CDPp2, 3, C0, C1, C2  CDPEQp3, 6, C1, C5, C7, 4

37. Coprocessor Data Transfers 37  Load (LDC) or store (STC) a subset of a coprocessors’s registers directly to memory  ARM is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred  Binary encoding

38. Assembler Format and Examples 38  Assembler format  LDC|STC{ }{L}, CRd, [Rn, ]{!} – pre-indexed  LDC|STC{ }{L}, CRd, [Rn], – post-indexed  Examples  LDCp6, C0, [r1]  STCEQLp5, C1, [r0], #4

39. Coprocessor Register Transfers 39  Communicate information directly between ARM and a coprocessor (MRC, MCR)  Binary encoding  Assembler format  MRC{ },, Rd, CRn, CRm{, }  MCR{ },, Rd, CRn, CRm{, }  Examples  MCRp14, 3, r0, C1, C2  MRCCSp2, 4, r3, C3, C4, 6

40. Breakpoint instruction (BKPT- architecture v5T only) 40  For software debugging purpose. Causes the processor to take a prefetch abort when the debug hardware unit is configured properly  Binary encoding  Assembler format  BRK  Examples  BRK