1. 17 Apr 2002 MCLARG Electronics Meeting News HEC Preshaper PRR passed on Thursday Apr 11 LECC02 (Workshop on LHC Electronics) will be held in Colmar, France 9-13 September. Abstract deadline: April 30 Design reviews for the boards in the front end crate have been scheduled in June. Instructions concerning agendas, documentation, etc. will be forthcoming. –June 13: Tower Builder Board and Tower Driver Board –June 18: Front End Board –June 19: Controller Board –June 21: Calibration Board Rack Layout Workshop was held on Feb 21. We have requested 21 racks in USA15 (not including L1 interface or TTC, which are in L1 request): ROD system: 8 HV system: 5 300 V. supplies+DCS: 8

2. 17 Apr 2002 MCLARG Electronics Meeting Reminder: LARG Electronics ASSO Focus is on interfaces between system and general organization One-day review with talks in the following areas: –Cold electronics (Srini) –FEC, Pedestal, Cooling (Helio) –Power supplies (300 V and DC-DC) (Helio) –HV systems (Helmut) –Radiation (Christophe) –Trigger sum transmission (Bill) –Overview of FEC interfaces (John) –Grounding and Shielding (Veljko) –ROD Functionality and Interfaces (Luc) –Documentation (Mauro) –Integration (TC) –Schedule (Bill) The speakers can expect interaction with the reviewers in the week(s) preceding the review. An advance copy of transparencies will be requested. The ASSO is scheduled for Monday of June LARG week.

3. 17 Apr 2002 MCLARG Electronics Meeting FEC Task Force Final Report Four meetings were held. Minutes of the meetings and a written final report are available on the LARG Electronics web page. Summary of findings: –Test will be carried out at BNL, with F. Lanni in charge –One half-crate (EMB configuration)will be fully instrumented with 14 FEBs 1 Controller Board 1 Calibration Board 1 Tower Builder Board 1 Monitoring Board –The FEBs will be loaded with toy calorimeters, placed at the end of cold cables –The readout will be made via a set of 8 ROD Demo Pus (6414 DSP), mounted on two VME motherboards (with VME readout only) –The remainder of the load on the power supply (for the other half crate) will be provided via dummy power loads

4. 17 Apr 2002 MCLARG Electronics Meeting FEC Task Force Report (2) In the EMB configuration, the following tests will be made: –Coherent noise –Timing jitter –Stability of downloaded data –Correspondence between L1 sums and data from main readout –Sensitivity to externally generated noise –Ground loop studies (between L1 receiver and FEC) –Stability of the system (baseline, noise, etc.) vs. temperature –Long term operation at high trigger rate –Effect of activity on SPAC bus on the data –Power cycling and sequencing studies –Performance at reduced loads on power supply –rf emission level –Trigger sum crosstalk –Tests of redundant features of the system –Tests with monitoring boards connected to ELMBs

5. 17 Apr 2002 MCLARG Electronics Meeting FEC Task Force Report (3) The first round of tests are those whose results are to be used for the PRR for the FEB. A second group of tests, whose results are to be used for other boards in the FEC are: –Trigger sum tests for EMEC standard crate –Trigger sum tests for EMEC special crate –Trigger sum tests for FCAL crate –Tests of FCAL calibration pulse distribution The HEC crate configuration will not be studied in the BNL tests, as this work can be done in the HEC test beam setup, where the proper input loads (cold preamps) are available. HEC-specific Board level tests, connected with HEC preshapers, will be carried out at Nevis or BNL. Tests are expected to begin in September 02 and last several months. The FEC boards and readout modules will then be shipped to CERN, to be used for the FCAL calibration run and later for tests in B180.

6. 17 Apr 2002 MCLARG Electronics Meeting FEC Task Force Members M. Citterio (ex officio) B. Cleland (chair) L. Hervas L. Kurchaninov X. Labroise B. Laforge F. Lanni H. Oberlack (ex officio) J. Parsons V. Radeka L. Serin C. de La Taille