1. Alessandro Gabrielli - SLAC - 15/02/081 Alessandro Gabrielli Physics Dep. & INFN Bologna -APSEL4D readout architecture -APSEL256x256D proposal -Emulator-Debugger APSEL4D -Feasibility on-chip data-compression

2. Alessandro Gabrielli - SLAC - 15/02/082 (2007) APSEL4D : ASIC designed and submitted 4096-MAPS matrix 100k std-cell area STM 130nm Area 7053  m  3034  m Architecture is data-driven, there is an on-line sparsification The hits are on-line associated with a 8-bit Time-Stamp The pixels, the MCs, the MRs and the MPs are numbered to define the 21-bit formatted output data - 128 columns  32 rows, - 32 MacroColumns (MC)  8 MacroRows (MR), - 256 MacroPixels composed of 4  4 pixels

3. Alessandro Gabrielli - SLAC - 15/02/083 Readout circuit with sparsification capabilities 4096-pixels Full-custom matrix 4096-pixels STD-cell-based matrix Main Features - 2 matrixes of 4096 pixels each - 1 made of MAPS, - 1 based on digital std-cells, - to be used one at a time, - Slow-Control for configuration, - on-line data sparsification, - 96 Pads - 2 clocks (over 50 MHz), - Stand_By if over-hit-rate 100k std-cells for the digital architecture + 4096 full-custom MAPS Nov. 2007 : ASIC designed and submitted

4. Alessandro Gabrielli - SLAC - 15/02/084 APSEL4D 2 macro-rows 8-bit x 256 MP 32 words 21 bits Matrix Area = 0.1 cm 2

5. Alessandro Gabrielli - SLAC - 15/02/085 NOT TO SCALE Up to 32 rows might be read out at a time Nov. 2007 : ASIC designed and submitted Wait for 1 reset cycle Example above requires 10 cycles to read out the hits [2MC  (4+1)]. Wait for 1 reset cycle

6. Alessandro Gabrielli - SLAC - 15/02/086 Nov. 2007 : ASIC designed and submitted 6 Hits on 1 column Parallel readout of the coordinates The 6 hits’ information are “stacked” into 1 circular Barrel independently of their original position in the column Time-Stamp Sparsifier

7. Alessandro Gabrielli - SLAC - 15/02/087 24-bits 0 1 31 2 READ Pointer WRITE Pointer 4 + 1 BARRELs: - circular and 32-word deep, - 24-bit words (now redundant), - never shift data (low power), - use pointers to identify the state, - can read 1 to 8 words at a time each, - can write 1 word at a time to ouput port, - empty their queues if in Stand_By status Nov. 2007 : ASIC designed and submitted Up to 8 hits at a time can be written into each BARREL Only 1 hit at a time is read out with a FIFO order

8. Alessandro Gabrielli - SLAC - 15/02/088 APSEL256  256D proposal ( 16 x APSEL4D ) 256  256-pixel Custom-Matrix 256  256-pixel Dummy-Matrix MC-Address-Decoder Sparsifier_0 Sparsifier_31 Barrel_0 Barrel_31 Latch-Enable Slow-Control Time-Stamp masks FastOrMasked LatchEnableMasked BC masks Sparsifier_Mid_0 Sparsifier_Mid_1 Sparsifier_Mid_2 Sparsifier_Mid_3 Barrel_Mid_0 Barrel_Mid_1 Barrel_Mid_2 Barrel_Mid_3 Sparsifier OUT Barrel Final Formatted Out The architecture is scalable, in principle Here master clock must be fast  200 MHz to cope with a hit-rate of 100MHz/cm 2, 20 x bkg-rate, (1.6 cm 2 leads to 160MHz/chip)

9. Alessandro Gabrielli - SLAC - 15/02/089 APSEL256  256D proposal Daisy-Chain for Series Data and Slow-Control or.. APSEL256x256 SC data APSEL256x256 Front-End fast Switch (Buffering,Trigger) data.. parallel front-end Data streams fast serialized via a “Switch” In any case the OutRate for a 4-chip architecture is 0.8  16Gb/s for a hit-rate range of 5  100MHz/cm 2

10. Alessandro Gabrielli - SLAC - 15/02/0810 APSEL4D Emulator-Debugger - APSEL4D compliant - static event control only: no real-time dynamic overlap (RDclk, BC, etc.) - no infinite loop test

11. Alessandro Gabrielli - SLAC - 15/02/0811 APSEL4D Emulator-Debugger File Generation: “auto-format” File Generation: “stimuli for VHDL/ASIC” File Generation: “expected output without TS” File Generation: “expected output with TS” File Load: “Monte Carlo” File Load : “auto-format” Control of “Masks” like in APSEL4D To be done N times.... to create N events Debug of N events:“expected vs VHDL/ASIC provided” 2 Options: “TS” and/or “order of events”

12. Alessandro Gabrielli - SLAC - 15/02/0812 Feasibility on-chip data-compression  8 hits per event:  4-hit cluster +  4-hit noise 3 examples out of 60-events (500-hits) to begin a study for an on-chip compressor BC  800ns, Rate = 100Mhit/cm 2 /s on 0.1 cm 2

13. Alessandro Gabrielli - SLAC - 15/02/0813 Feasibility on-chip data-compression : 500 Out Data created via the emulator XOR function between two consecutive valid 20-bit Out Data

14. Alessandro Gabrielli - SLAC - 15/02/0814 Feasibility on-chip data-compression : 500 Out Data RANDOMLY generated XOR function between two consecutive valid 20-bit Out Data

15. Alessandro Gabrielli - SLAC - 15/02/0815 Conclusion APSEL256x256D is feasible ! - readout viewpoint, ”Custom Matrix is another point” On-chip compression is under feasibility study. - Should be simple and fast, - Requires a fast encoder to create a variable-lenght bit stream - Estimation: - RDclk160 MHz ( = 4  RDclk APSEL4D ), - Rate 100 Mhit/s/cm 2 ( = Rate APSEL4D ), - Compression Factor 2  3 ( = 2  3  Comp. Fact. APSEL4D ), … readout throughput rises from to-date APSEL4D 40 Mhit/s to 8  12  40 = 320  480 Mhit/s The architecture might read larger APSELXX ASICs with sensitive area of 3.2  4.8 cm 2, that is 32  48 times APSEL4D, while APSEL256x256D is “only” 16 times APSEL4D