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Politecnico di Milano & INFN 1 SVT FE 04/11/2011 Update on analog design for L4-L5 B.Nasri, P.Trigilio, L.Bombelli, C.Fiorini SVT FE confcall – 04/11/11.

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Presentation on theme: "Politecnico di Milano & INFN 1 SVT FE 04/11/2011 Update on analog design for L4-L5 B.Nasri, P.Trigilio, L.Bombelli, C.Fiorini SVT FE confcall – 04/11/11."— Presentation transcript:

1 Politecnico di Milano & INFN 1 SVT FE 04/11/2011 Update on analog design for L4-L5 B.Nasri, P.Trigilio, L.Bombelli, C.Fiorini SVT FE confcall – 04/11/11 Activity: study and optimization of input MOSFET ENC estimations preliminary layout evaluations

2 Politecnico di Milano & INFN 2 SVT FE 04/11/2011 Electronics noise evaluation with Cadence (IBM 130nm) Detector (Cd, Rs) Charge preamplifier (ideal) Shaping amplifier (CR-(RC) 2 ideal) (NMOS, PMOS) Considered parameters for the detectors: Layer 4: Rs=234 , Cd=52.6pF Layer 5: Rs=300 , Cd=67.5pF Rs/3 considered for noise (and compared with distributed parameters model)

3 Politecnico di Milano & INFN 3 SVT FE 04/11/2011 Usefulness of direct Cadence simulations of ENC Comparison of FETs contributions to ENC not fully evident from noise spectra only

4 Politecnico di Milano & INFN 4 SVT FE 04/11/2011 NMOS, Layer 4 Ibias=500µA and Tp=1µs L= 150nm ~ 500nm ; W=5mm ~ 15mm Minimum ENC of FET relates to L=300nm; ENC_FET_total= 307.2 e rms @ W=9mm

5 Politecnico di Milano & INFN 5 SVT FE 04/11/2011 L (nm)150200250300350400450500 ENC_FET_fn (e rms)267.2197.4163.9145.3138.7131.6126.1123 ENC_FET_thermal (e rms)306.9276267268.7286.2298.5310.8326.1 Table 1. ENC generated by thermal and Flicker noise of NMOS FET at Layer 4 and W=9mm Flicker Thermal

6 Politecnico di Milano & INFN 6 SVT FE 04/11/2011 Sweeping the bias current @ optimum L and W (L=300nm, W=9mm) and Tp=1µs

7 Politecnico di Milano & INFN 7 SVT FE 04/11/2011 Sweeping the peaking time @ optimum L and W (L=300nm, W=9mm) and Ibias=500µA

8 Politecnico di Milano & INFN 8 SVT FE 04/11/2011 NMOS, Layer 5 Ibias=500µA and Tp=1µs L= 150nm ~ 500nm; W=5mm ~ 15mm Minimum ENC of FET relates to L=300nm; ENC_FET_total= 379.6 e rms @ W=9mm L (nm)150200250300350400450500 ENC_FET_fn (e rms)334.2246.3203.8179.8164.9160.8148142.8 ENC_FET_thermal (e rms)383.8344.4333332.6364.7 365378.5 Table 2. ENC generated by thermal and Flicker noise of NMOS FET at Layer 5 and W=9mm

9 Politecnico di Milano & INFN 9 SVT FE 04/11/2011 PMOS, Layer 4 Ibias=500µA and Tp=1µs Minimum ENC of FET relates to L=150nm; ENC_FET_total= 359 e rms @ W=7mm L (nm)150200250300350400450500 ENC_FET_fn (e rms)69.4659.1852.7948.4945.4543.2241.5240.22 ENC_FET_thermal (e rms)352.3366385.6404.3421.5437.8453.6469.2 Table 3. ENC generated by thermal and Flicker noise of PMOS FET at Layer 4 and W=7mm

10 Politecnico di Milano & INFN 10 SVT FE 04/11/2011 PMOS, Layer 5 Ibias=500µA and Tp=1µs Minimum ENC of FET relates to L=150nm; ENC_FET_total= 451 e rms @ W=7mm L (nm)150200250300350400450500 ENC_FET_fn (e rms)87.277465.860.256.1553.1250.7848.93 ENC_FET_thermal (e rms)442.6458480.7501.8520.7538554.7570.9 Table 4. ENC generated by thermal and Flicker noise of PMOS FET at Layer 5 and W=7mm

11 Politecnico di Milano & INFN 11 SVT FE 04/11/2011 Comparison of NMOS and PMOS (without Rs) Layer 4 Layer 5

12 Politecnico di Milano & INFN 12 SVT FE 04/11/2011 Overall noise (including Rs) Layer 4 Layer 5 Tp= 1us blue/green are total noise, others lines are Rs only, for reference

13 Politecnico di Milano & INFN 13 SVT FE 04/11/2011 Layer 4 Layer 5 Ibias= 500uA blue/green are total noise, others lines are Rs only, for reference

14 Politecnico di Milano & INFN 14 SVT FE 04/11/2011 Summary of noise evaluations Contribution of Rs on the overall noise quite significant Noise from NMOS slightly better than in PMOS ‘Optimum size’ PMOS smaller than NMOS (W: 7 vs. 9mm, smaller L) Compromise L however could be chosen (e.g. 200nm) NMOS vs. PMOS choice also depending on cleaner power line (more clean GND for NMOS or VDD for PMOS?) Choose input MOS and start of preamplifier design Further noise evaluations with respect to shaping amplifier design

15 Politecnico di Milano & INFN 15 SVT FE 04/11/2011 46um 170um 480um 350um 370um Preliminary area estimations Peaking time = 1us Very simple implementation with physical R,C 46um MIMs cap std cap

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