1. 1 COMP541 Video Monitors Montek Singh Mar 11, 2016

2. Reminder: Good Verilog Practices  Best to use single clock for all FFs Make all signals synchronous to one clock Make all signals synchronous to one clock  No: @(posedge button) etc.  Yes: @(posedge clock) Avoids “weird” and frustrating problems Avoids “weird” and frustrating problems  Multiple modules Tested individually Tested individually Top level has input and outputs Top level has input and outputs  One module per file Just to make it easier to follow and test Just to make it easier to follow and test 2

3. VGA Monitors 3

4. 4 How Do Monitors Work?  Origin is TV, so let’s look at that LCDs work on different principle, but all signaling still derived from TV of 1940s LCDs work on different principle, but all signaling still derived from TV of 1940s  Relies on your brain to do two things Integrate over space Integrate over space Integrate over time Integrate over time

5. Many Still Images  Video (and movies) are a series of stills If stills go fast enough your brain interprets as moving imagery If stills go fast enough your brain interprets as moving imagery  50-60 Hz or more to not see flicker –“1 Hz” means once per second In fact, even if the scene does not change… In fact, even if the scene does not change…  … a single “still” image is displayed repeatedly over time  Why? Phosphor persistence varies 5

6. Cathode Ray Tube (CRT) 6 From wikipedia: http://en.wikipedia.org/wiki/Cathode_ray_tube

7. Deflection Coils 7

8. Simple Scanning TV  Electron beam scans across  Turned off when Scanning back to the left (horizontal retrace ----) Scanning back to the left (horizontal retrace ----) Scanning to the top (vertical retrace ____) Scanning to the top (vertical retrace ____) 8

9. Scanning: Interlaced vs. Progressive  (Some) TVs use interlacing Every other scan line is swept per field Every other scan line is swept per field Two fields per frame (30Hz) Two fields per frame (30Hz) Way to make movement less disturbing Way to make movement less disturbing  Computers use progressive scan Whole frame refreshed at once Whole frame refreshed at once 60Hz or more, 72Hz looks better 60Hz or more, 72Hz looks better  Similar notation used for HD i = interlaced (1080i) i = interlaced (1080i) p = progressive (1080p) p = progressive (1080p) which better? which better? 9

10. Color  Three colors of phosphor three beams, one each for the three phosphors three beams, one each for the three phosphors Black: all beams off Black: all beams off White: all beams on White: all beams on 10 Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

11. What about LCD?  How do LCD monitors work? internals are very different internals are very different  no beams, tubes  made up of tiny LCD cells However, external signaling is the same! However, external signaling is the same!  for compatibility  Same goes for micro-mirror projectors tiny mirrors (one/pixel) that allow light through or send it out of the way tiny mirrors (one/pixel) that allow light through or send it out of the way possible to change pixels selectively possible to change pixels selectively 11

12. 12 VGA Signaling  Timing signals horizontal sync (hsync) & vertical sync (vsync) horizontal sync (hsync) & vertical sync (vsync)  Color values: R, G, B total 8 bits for Nexys 3 (rrrgggbb), 12 bits for Nexys 4 (rrrrggggbbbb) total 8 bits for Nexys 3 (rrrgggbb), 12 bits for Nexys 4 (rrrrggggbbbb) Nexys 4 digital to analog converter

13. VGA Timing  You supply two pulses hsync and vsync hsync and vsync allow the monitor to lock onto timing allow the monitor to lock onto timing One vsync per frame One vsync per frame One hsync per scan line One hsync per scan line  hsync does not stop during vsync pulse 13 Image from dell.com

14. Horizontal Timing Terms  Horizontal timing: hsync pulse hsync pulse Back porch (left side of display) Back porch (left side of display) Active Video Active Video  Video should be blanked (not sent) at other times Front porch (right side) Front porch (right side) 14

15. Horizontal Timing 15 640 Horizontal Dots Horiz. Sync Polarity NEG Scanline time (A) 31.77 us Sync pulse length (B) 3.77 us Back porch (C) 1.89 us Active video (D) 25.17 us Front porch (E) 0.94 us Image from http://www.epanorama.net/documents/pc/vga_timing.html This diagram shows video as a digital signal. It’s not – video is an analog level. us = microsecond

16. Vertical Timing (note ms, not us) 16 Vert. Sync Polarity NEG Vertical Frequency 60Hz Total frame time (O) 16.68 ms Sync length (P) 0.06 ms Back porch (Q) 1.02 ms Active video (R) 15.25 ms Front porch (S) 0.35 ms

17. Timing as Pixels  Easiest to derive all timing from single-pixel timing  How “long” is a pixel? Active video / number of pixels Active video / number of pixels 25.17 us / 640 = 39.32ns 25.17 us / 640 = 39.32ns Conveniently close to 25 MHz – just use that Conveniently close to 25 MHz – just use that Actual VESA spec is 25.175 MHz Actual VESA spec is 25.175 MHz 17

18. The overall picture 18 (Picture from http://www.pyroelectro.com)

19. Standards  640 x 480 (sometimes x 60Hz) is “VGA” I will give you spec sheets in lab I will give you spec sheets in lab  You can try for 800x600 at 60 Hz (40 MHz exactly) or 800x600 at 72 Hz (50 MHz exactly) or 800x600 at 72 Hz (50 MHz exactly)  Note that some standards have vsync and hsync positive true, some negative true choose correct polarity choose correct polarity determine by experimentation! determine by experimentation! 19

20. Color Depth  Voltage of each of RGB determines color Nexys 4: Nexys 4:  4-bit for red, green and blue All on for white All on for white 20 Nexys 4

21. Lab 8 1. Make Verilog module to generate hsync, vsync, horizontal count, vertical count, and signal to indicate active video hsync, vsync, horizontal count, vertical count, and signal to indicate active video 2. Use higher-level module to drive RGB using counts gated by active Just do something simple (stripes, checkerboard, diagonals) Just do something simple (stripes, checkerboard, diagonals) 3. Later we will use memory addressed by counts to make a terminal  Notes: Be careful about the “Sync Polarity” Be careful about the “Sync Polarity”  A “1” means a downward going pulse –sync signal is normally high, but goes low during the pulse  A “0” means an upward going pulse Use my self-checking text bench! Use my self-checking text bench!  simulates my VGA driver …  … and compares your outputs with mine  flags any mismatches 21

22. 22 What do you need for VGA?  Think first Need counter(s)? Need counter(s)? Will you need a state machine? Will you need a state machine?  Sketch out a design Block diagram Block diagram  Test individually in lab  Keep in mind Verilog has all these operators (and more; see Verilog ref.) Verilog has all these operators (and more; see Verilog ref.) ==,, = ==,, =

23. VGA Links  VGA Timing Recommended: http://tinyvga.com/vga-timing Recommended: http://tinyvga.com/vga-timinghttp://tinyvga.com/vga-timing http://www.epanorama.net/documents/pc/vga_timing.html http://www.epanorama.net/documents/pc/vga_timing.html http://www.epanorama.net/documents/pc/vga_timing.html  Interesting http://www.howstuffworks.com/tv.htm http://www.howstuffworks.com/tv.htm http://www.howstuffworks.com/tv.htm http://computer.howstuffworks.com/monitor.htm http://computer.howstuffworks.com/monitor.htm http://computer.howstuffworks.com/monitor.htm http://www.howstuffworks.com/lcd.htm http://www.howstuffworks.com/lcd.htm http://www.howstuffworks.com/lcd.htm http://plc.cwru.edu/ http://plc.cwru.edu/ http://plc.cwru.edu/ 23