1. 1 ASICS - Status Ivan Perić University of Heidelberg Germany

2. 2 ASICs on the module DHP DCD SWITCHER DCE

3. 3 SWITCHERB Three SWITCHER versions have been designed SWITCHERB in 350nm AMS technology (tested) SWITCHERB18 in 180nm AMS technology (tested) SWITCHERB18G (“G” for gated-mode) in 180nm AMS (submitted in May) All three chips are pin- and control-signal- compatible to each other SWITCHERERB18G is an extended SWITCHER version that supports the gated-mode operation We have designed a probe station based needle card system for serial tests Yield is about 80% (both tested versions)

4. 4 SWITCHERB and SWITCHERB18 SWITCHERB in 350nm AMS (radiation tolerant layout) SWITCHERB18 in 180nm AMS (standard layout)

5. 5 SWITCHERB - Plans Will be done soon: Irradiations of SWITCHERB18: SWITCHERB in 350nm has been layout-ed in the rad-hard “fashion” i.e. with enclosed gate- transistors SWITCHERB18 uses only the standard layout – due to a thinner gate oxide we expect a sufficient radiation tolerance without the rad-hard layout DCDB (in 180nm UMC technology) also uses the standard layout in its digital part September 2012 – testing of the gated mode in test beam Bumping issues: So far we use the gold+solder- bump technique developed in HD We will check the possibility to use a commercial bumping The final chip will require only small changes

6. 6 DCD The second version of DCDB (DCDBv2) has been tested at the full speed stand alone and with PXD (100ns sampling rate) The chip has been successfully used in several test beams, mostly at a reduced speed due to FGPA issues The typical noise is around 60nA – assuming realistic DEPFET gq about: 120e The analog mode common mode correction (ACMC) is still under investigation – different bump- /wire-bond adapters are needed for these tests - complicated First results (ACMC) with a small size test chip are good We have designed a probe-station-based needle card system for serial tests The card uses special soft needles for bumped chips Yield is about 80% (DCDBv2) We do not observe broken channels – about one per cent of the channels are somewhat more sensitive to the bias settings than the “good channels”, not an serious issue

7. 7 DCD DCD test at 100MHz Characteristics of 256 ADCs Average noise ~ 60nA (noise on standard PCB ~ 40nA) 180nA 260nA

8. 8 Hybrid Board with DCDBv2 and thin PXD at full speed The histogram of all pixel amplitudes – the signal dispersion is an (overestimated) measure of noise RMS: 1.5 ADC units (about 80nA) Cluster signal is a bit overestimated due to a bug (fixed later) Realistic value for cluster signal ~ 40 ADC units – SNR 26 Preliminary!!!

9. 9 DCD - Plans Irradiation of DCDBv2 is planned with Bonn. We have already irradiated the first DCD prototype with almost identical analog parts – we do not expect any “surprises” The final version requires several non-complicated changes: Replacing of the standard memory cells with the SEU tolerant cells in the global configuration register Adding of the read-back possibility to monitor SEU rate Adding of an additional offset correction in the analog channels to cope with DEPFET mismatch Implementing of a test multiplexer to allow probe-station tests of the entire chip (only ½ of the channels can be tested presently!) Implementing of a temperature-stable reference current generator Minor layout changes for better yield (should eliminate sensitive channels) Amplifier gain should be adjusted to achieve a higher dynamic range (the gain is programmable) Minor changes in the ACMC network Optionally – implementation of power regulators for AmpLow and RefIn voltages – the regulators will be tested soon – they are implemented on a smaller test chip that we already received

10. 10 DHP DHP in IBM 90nm The full-size DHP chip (DHP0.2) has been designed in 90nm IBM technology The chip has been successfully tested (without DCD): Successful data transmission through a 15m cable at 1.6GBit/s Data processing works: pedestal subtraction, CM correction, hit finding… SWITCHER sequencer tested The next step: Tests with DCD and DHP together DHPT in TSMC 65nm Since IBM has stopped offering the technology for small customers, DHP will be redesigned in 65nm TSMC technology Three DHP test chips in 65nm TSMC have been investigated Chip A: PLL and CML Chip B: RAM Chip C: DAC and Reference PLL and CML work - successful transmission at 16GBit/s through 10-15m cable RAM has been tested and irradiated at CERN PS to check SEU tolerance SEU x-section for RAM estimated ~ 10 -13 cm -2 for 24GeV protons We expect 10 4 neutrons/cm 2 s from background -> if we assume 10 6 bits in total, we will have a flip every 15 minutes – can be coped easily Chip works up to very high doses ~ 800MRad (!) Full size chip (DHPT 1.0, TSMC 65nm) should be designed & submitted by end 2012

11. 11 DHP DHP0.2 Test system DUT DHH emulator DHP0.2 on WB adapter DHPT in test beam DHP0.2 Eye diagram DHPT chips

12. 12 DCE DCE3 minichip (TSMC 65nm) with 256 clustering nodes back from production Bonding adapter ready Clustering carrier board (CCB) will be ready in September (design finished – the board is in production) CCB uses 2 low cost FPGA connected via 2 serial links (Aurora) to the DHH 14(!) layer PCB DDR3 socket for DCE3 board (8 layers) DCE-adapter will be directly bonded to the DCE board CCB firmware (FPGA, monitoring C) development started with DHH-CCB simulation model CCB

13. 13 SWITCHERB18G for gated-mode operation SWITCHERB18G that supports gated-mode operation has been designed in May and will be back from production beginning of September 2012 The chip is pin- and signal-compatible to the standard SWITCHER versions In standard mode operation the equal signal sequence is used as presently Gated-mode operation requires a slightly modified sequence

14. 14 SWITCHERB18G block schematic LV Ctr. SERIN SEROUT STRG STRC HV Chan. GHi, GLo CHi, CLo CLK FF StrGB CCLK or StrClr Volt. Regulator JTAG Slow control NoisyEn3 NoisyEn0 Gated-mode control 32 high-voltage channels (level shifters) that generate the high-voltage signals. Low voltage control block (based on shift register) used to select the high-voltage channels. Two voltage regulators that generate 4 high-voltage supplies each Fast control uses four signals: CLK, Sin, StrGate, StrClear Gated mode control

15. 15 SWITCHERB18G The channels are divided into 4 groups, 8 channels each These groups enter the gated phase one after another to avoid high clear currents when clear signals are set high The controlling of the SWITCHER is performed using 4 signals: StrClr, StrGate, CLK and Sin, as presently The activating of the gated phase is initiated by a signal combination that in normal operation does not occur During the gated phase, the LV control logic of the channel operates in a slightly different way than during the normal phase – the control sequence should be slightly adjusted Two gated readout modes are supported Mode 1: Readout doesn’t stop during blind phase Mode 2: Readout is stopped during blind phase

16. Waveforms – readout during blind phase off gate on CLK StrClr StrGate gate Noisy Enable#1 S S S S S S clr Clr1 GateOn1 Clr2 GateOn2 Clr3 GateOn3 Clr4 GateOn4 Clr5 GateOn5 Clr6 GateOn6 Blind mode Bl. mode Blind mode Noisy Seqence Blind mode True reset clr Noisy Enable#2 gate Noisy Bunches

17. Waveforms – no readout during blind phase off on CLK StrClr StrGate Noisy Enable#1 S S S Clr1 GateOn1 Clr2 GateOn2 Clr3 GateOn3 Clr4 GateOn4 Clr5 GateOn5 Clr6 GateOn6 Blind mode Noisy Seqence Blind mode True reset Noisy Enable#2 SSS ABCD ETrue reset X Noisy Bunches

18. 18 SWITCHERB18G - layout 3625  m 1470  m JTAG HV channel Volt. Regulator LV ctrl. Prot. Diodes LVDS receivers Bump pads

19. Simulations 19 We simulate the gated mode SWITCHER with readout during blind phase Blind phase Clr Gate On Ch#0 Ch#7

20. Simulations 20 We simulate the gated mode SWITCHER without readout during blind phase Blind phase Clr Gate On Ch#0 Ch#6 Ch#7

21. Simulations of the Module with 6 SWITCHERs 21 Ideal voltage sources – in reality large decoupling capacitors Transmission lines – distributed LRC elements – simulates flex Decoupling capacitors on the module – all reverenced to source with serial R=0.25Ohm Source, GateHi/Lo, ClrHi/Lo, gnd,vdd 200Ohm resistors simulate DCDs vdd 196 SWITCHER channels256 “4-columns” 196 “4-rows” 3.76ns, 38Ohm Signal speed: 1/(lc) 0.5 Impedance: l/c Transmission line

22. Source Drain Clear Gate ClearHi ClearLo GateHi GateLo Drift To all To all (except drain) CCG 37 2565 10kOhm 200Ohm 3.76ns, 38Ohm 6x32 rows Simplified equivalent circuit of the module CCGint row

23. Gate Clear Channel0 Channel1 Channel2 Channel3 Source Dirty Bunch Phase Results 1: Decoupling 10nF Drain current

24. Dirty Bunch Phase Results 1: Decoupling 10nF Drain current Signal no plateau Pedestal

25. Dirty Bunch Phase Results 1: Decoupling 10nF Drain current Signal no plateau Pedestal Equal pedestals

26. Gate Clear Channel0 Channel1 Channel2 Channel3 Source Dirty Bunch Phase Results 2: Decoupling 100nF Drain current

27. Dirty Bunch Phase Results 2: Decoupling 100nF Drain current Pedestal Signal Better plateau?

28. Dirty Bunch Phase Results 2: Decoupling 100nF Drain current Signal Better plateau? Pedestal Equal pedestals

29. 29 Conclusions New SWITCHERB18v2 that supports gated-mode operation has been designed and submitted The chip will be available beginning of September The full size DHP0.2 has been successfully tested without DCD Tests with DCD will be done soon DHPT test chips in 65nm TSMC technology have been successfully tested as well – RAM, 1.6GBit/s data transmission and PLL work. The RAM chip has been irradiated up to 800MRad to test SEU rate. The SEU tolerance is good and sufficient DCDv2 works fine Ordering of larger number of DCD chips is relatively cheap - 30Chips – 2k€ Preliminary module-level simulations show that gated mode operation is possible DCE boards have been designed and are in production. First tests in September 2012

30. 30 Backup slides

31. 31 High voltage channel High-voltage channel - main parts: U-I converter C High-voltage power transistors Tp and Tn. Floating-logic gate control blocks. Low power consumption – sleep mode Break before make feature C 0V 1.8V C/GHI C/GLO 1.8V offon off HVOut LVIn Sleep LV ctrl. gate control block Tp Tn C/GLO0 C/GHI0 GNDD VDDD

32. 32 Regulator hi hi0 lo0 lo ref sub 1.8 Power T

33. 33 High voltage channel – transistor schematic TdiffnTdiffp TdionTdiop Idiff Tp Tn Toffp Tonn Tswn ToffnTonp Tswp Tdion2 n1n2 n3 D1 Inv3 D2 Buff2 Buff1 HVOut LVIn C/GHI C/GHI0 C/GLO0 C/GLO GNDD VDDD