1. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Advanced Digital Design with the Verilog HDL Chapter 1 ~ 5

2. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Contents  Introduction to Digital Design Methodology  Review of Combinational Logic Design  Fundamentals of Sequential Logic Design  Introduction to Logic Design with Verilog  Logic Design with Behavioral Models of Combinational and Sequential Logic

3. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Introduction to Digital Design Methodology

4. Verilog 강의자료 REAL TIME ARCHITECTURE LAB CHAPTER 2 Review of Combinational Logic Design

5. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Review of Combinational Logic Device  Combinational Logic and Boolean Algebra  Boolean Algebra  Theorems for Boolean Algebraic Minimization  Representation of Combinational Logic  Sum of Products Representation  Product of Sums Representation  Simplification of Boolean Expressions  Karnaugh Maps (SOP / POS form)  Glitches and Hazards  Eliminations of Hazards  Building Blocks for Logic Design  Multiplexers / Demultiplexers  Encoder / Decoder

6. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Combinational Logic and Boolean Algebra X X 0 1 X 1 0 T ruth Table Gate X Inverter Gate X Y Truth Table Y 0 1 0101 X 0 0 1111 Z 0 0 0101 Z And X Y Z Truth Table X 0 0 1 1 Y 0 1 0 1 Z 0 1 1 1 Gates Or X Y Truth TableGates X 0 0 1 1 Y 0 1 0 1 Z 1 1 1 0 Z Nand Gates X Y Z Truth Table X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 0 Nor TruthTable X 0 0 1 1 Y 0 1 0 1 Z 0 1 1 0 Gates X Y Z Xor

7. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Combinational Logic and Boolean Algebra Laws of Boolean AlgebraSOP FormPOS Form Combinatinos with 0,1 a + o = aa ·1 = a a + 1 = aa ·0 = 0 Commutative a + b = b + aab = ba Associative (a + b) + c = a +(b + c) = a + b + c (ab)c = a(bc) = abc Distributive a(b + c) = ab + aca + bc = (a + b)(a + c) Idempote a + a = aa ·a = a Involution (a’)’= a Complementarity a + a’= 1a ·a’ = 0

8. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Combinational Logic and Boolean Algebra TheoremSOP FormPOS Form Logical Adjacency ab + ab’= a(a + b)(a + b’) = a Absortion a + ab = a ab’ + b = a + b a + a’b = a + b a(a + b) = a (a + b’)b = ab (a’+b)a = ab Multiplication and Factoring (a + b)(a’+c) = ac + a’bab + a’c = (a + c)(a’+ b) Consensus ab + bc + a’c = ab + a’c (a + b)(b + c)(a’+ c) = (a +b)(a’+ c)

9. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Representation of Combinational Logic  Sum of Products Representation ex) full-adder sum = a’b’c_in + a’bc_in’ + ab’c_in’ + abc_in c_out = a’bc_in + ab’c_in + abc_in’ + abc_in  Product of Sums Representation ex) full-adder sum = (a+b+c_in)(a+b’+c_in’)(a’+b+c_in’)(a’+b’+c_in) c_out = (a+b+c_in)(a+b+c_in’)(a+b’+c_in)(a’+b+c_in) *Method of getting SOP Representation from POS Representation 1. get sum’ from sum 2. express sum by complementing sum’ 3. use De Morgan’s Law each term

10. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Simplification of Boolean Expressions  SOP : 2-level AND,OR logic circuit.  K-map ( SOP )  use value-1 and don’t care  K-map ( POS )  use value-0 and don’t care  use De Morgan’s Law  K-map ( Don’t care )  fast by using don’t care

11. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Glitches and Hazards  Glitches  delays of actual implementation and circuit structure  Hazards  glitch caused by input signal  Static Hazards  0-hazard, 1-hazard  caused by differential propagation delays ( Figure 2-32,33 )  Eliminate Static Hazards  use k-map and check Redundant cube ( Figure 2-34 )  Dynamic Hazards  caused by many static-hazard  Eliminate Dynamic Hazards  transform circuit into a two-level form  detect and eliminate all static hazards

12. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Building Blocks for Logic Design  Multiplexers Data_Out = Data_In[ Address[k] ] Address[m-1:0] Data_Out Data_In[0] Data_In[n-1]

13. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Building Blocks for Logic Design  Demultiplexers Data_Out[n-1:0] = Data_In[Address[k], k = 0:m-1 ] Address[m-1:0] Data_In Data_Out[0] Data_Out[n-1]

14. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Building Blocks for Logic Design  Encoders n-bit inputs m-bit outputs n = 2 m Data_InData_Out /n/n /m/m

15. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Building Blocks for Logic Design  Decoders m-bit inputs n-bit outputs n = 2 m Data_InData_Out /m/m /n/n

16. Verilog 강의자료 REAL TIME ARCHITECTURE LAB CHAPTER 3 Fundamentals of Sequential Logic Device

17. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Fundamentals of Sequential Logic Device  Storage Elements  Latches  Transparent Latches  Flip-Flops  D-Type Flip-Flop  Buses and Three-State Devices  Design of Sequential Machines  A Mealy-type FSM for Serial Line-code Conversion  A Moore-type FSM for Serial Line-code Conversion

18. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Storage Elements  NOR gates S-R Latches SRQ next Q’ next 00QQ’Q’Hold 0101Reset 1010Set 1100 Not allowed

19. Verilog 강의자료 REAL TIME ARCHITECTURE LAB A Transparent Latch 10 20 30 40 50 Data Enable Q_out 1 1 1

20. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Flip-Flops DQQ next 000 010 101 111

21. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Buses and Three-State Devices

22. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Design of Sequential Machines  Edge-triggered  rising-edge  falling-edge  State Machine  Finite State Machine ( FSM ) : always finite  number of states : n-bits word state => 2 n states  Mealy Machine  outputs and the next state depend on the present state + inputs  Moore Machine  outputs depends on the present state

23. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Mealy Machine

24. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Moore Machine

25. Verilog 강의자료 REAL TIME ARCHITECTURE LAB CHAPTER 4 Introduction to Logic Design with Verilog

26. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Introduction to Logic Design with Verilog  Structural Models of Combinational Logic  Verilog Primitives and Design Encapsulation  Verilog Structural Models, Module Ports, Some Language Rules  Top-Down Design and Nested Modules  Design Hierarchy and Source-Code Organization  Vectors in Verilog, Structural Connectivity  Logic System, Design Verification, and Test Methodology  Four-value Logic and Signal Resolution in Verilog  Test Methodology  Signal Generators for Testbenches  Testbench Template  Propagation Delay  Inertial Delay, Transport Delay  Truth Table Models of Combinational and Sequential Logic

27. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Structural Models of Combinational Logic  Verilog Primitives and Design Encapsulation  primitives : 26 predefined models of combinational logic gates  ex) and, nand, or, nor, xor, xnor, buf, not, bufif0, bufif1 …  Example : 1-bit half adder  Verilog description of a half adder and schematic module Add_Half(sum,c_out,a,b); inputa,b; outputc_out,sum; xor(sum,a,b); and(c_out,a,b); endmodule *Tips: The output port of primitives must be first in the list of ports.

28. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Verilog Structural Models  a module name accompanied by its ports  a list of operational modes of the ports  an optional list of internal wires  other variables used by the model  a list of interconnected primitives and other modules  the format of verilog module module my_design ( module_ports); //Declarations of ports //Functional details endmodule

29. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Module Ports / Some Language Rules  mode of a port determines the direction  input, output, inout  match ports in each module  outputs are the left-most entries in the port list of a primitives  verilog is a case-sensitive languages  C_out_bar != C_OUT_BAR  variable may not begin with a digit or $  variable may be up to 1024 characters long  identifier must not use white space  each line of text must terminate with a “;” except endmodule  comments “//”, “/* */”

30. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Top-down Design and Nested Modules  Top-down design is used in the most modern methodology.  Nested modules are the Verilog mechanism supporting top-down design.  Example : 1-bit full adder module Add_full_0_delay (sum, c_out, a, b, c_in); inputa, b, c_in; outputsum, c_out; wirew1, w2, w3; Add_Half M1 (w1, w2, a, b); Add_Half M2 (sum, w3, c_in, w1); or (c_out, w2, w3); endmodule *Tips: The ports of a module may be listed in any order. An instantiated module must have an instance name.

31. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Design Hierarchy and Source-code Organization * 4-bit RCA Hierarchy * 1-bit full adder * 1-bit half adder

32. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Vectors in Verilog / Structural Connectivity  sum[3:0] represent 4-bits from sum  decimal 4 = 0100 binary, sum[2] = 1  Use nets to establish structural connectivity.  An undeclared identifier is treated by default as a wire  Example : Formal and actual names for port association … Add_half_0_delay M1 (.b(b),.c_out(w2),.a(a), sum(w1) ); Add_half_0_delay M1 (w1, w2, a, b); … module Add_half_0_delay (sum, c_out, a, b);

33. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Logic System, Design Verification, and Test Methodology  Four-Value Logic and Signal Resolution in Verilog  1, 0, x, z  0,1 : true or false  x : unknown value  z : high impedance ( disconnected or no-value )  Test Methodology  registers connect to inputs of top module.  outputs of top module connect wires.  UUT : unit under test ( top module) `timescale 1ns/1ns module _t_Add_Half(); wiresum,c_out; regc; regb; Add_Half M1 (sum,c_out,c,b); initial begin #10; c=0; b=0; #10; b=1; #10; c=1; #10; b=0; $stop; end endmodule

34. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Logic System, Design Verification, and Test Methodology (Cont)  Signal Generators for Testbenches  `timescale 1ns/1ns  “initial” keyword  begin ~ end  #10;  c=0; b=0;  reg ( input ), wire ( output )  Event-Driven Simulation  UUT called when value c or b is changed.  Testbench Template  important tool in the design of an ASIC. module _t_DUTB_name (); reg...; wire....; parameter UUT_name M1_instance_name (UUT ports); initial begin... // generate wave forms here end endmodule

35. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Propagation Delay  All primitives and nets have a default propagation delay of 0.  Propagation delay  Transport Delay  Inertial Delay  physical behavior of a signal transition is said to have inertia  caused by resistance, capacitance…  Verilog deals the propagation delay as the inertial delay.  Example : propagation delay = 2

36. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Truth Table Models of Combinational and Sequential Logic  Verilog supports truth-table models of combinational and sequential logic.  UDP : user defined primitive  widely used : faster and require less storage than modules.  The output of a user-defined primitive must be a scalar. primitive mux_prim (mux_out, select, a, b) output mux_out; input select, a, b; table //selectab:mux_out 000:0; 001:0; 00x:0; 010:1; 011:1; 01x:1;... endtable endprimitive

37. Verilog 강의자료 REAL TIME ARCHITECTURE LAB CHAPTER 5 Logic Design with Behavioral Models of Combinational and Sequential logic

38. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Logic Design with Behavioral Models of Combinational and Sequential logic  Behavioral Modeling  Propagation Delay and Continuous Assignments  Cyclic Behavioral Models of Flip-Flops and Latches  Cyclic Behavior and Edge Detection  Behavioral Models of Multiplexers, Encoders, and Decoders  Algorithmic State Machine Charts for Behavioral Modeling  ASMD Charts  Shift Register

39. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Behavioral Modeling / Data Types  ASICs have several milion gates on a single chip.  described by functionality  reg: 1bit  integer : 32bit  wire : 1bit

40. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Propagation Delay and Continuous Assignments  assign : continuous assignment.  assign y_out = a + b;  assign and_result = a & b;  assign not_result = ~a; module compare 2_CA0 (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0); input A1, A0, B1, B0; output A_lt_B, A_gt_B, A_eq_B; assign A_lt_B = (~A1)&B1 | (~A1) & (~A0) & B0 | (~A0) & B1 &B0; assign A_gt_B = A1 & (~B1) | A0 & (~B1) & (~B0) | A1 & A0 & (~B0); assign A_eq_B = (~A1) & (~A0) & (~B1) & (~B0) | (~A1) & A0 & (~B1) & B0 | A1 & A0 & B1 & B0 | A1 & (~A0) & B1 & (~B0); endmodule

41. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Cyclic Behavioral Models of Flip-Flops and Latches  Cyclic Behavior to model edge-sensitive functionality.  “always” : corresponding to an edge-triggered flip-flop  always @ ( posedge clock ) begin … end  always @ ( negedge clock ) begin … end  non-blocking operator “ <= “  cyclic behavior must be a declared register-type variable

42. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Comparator Model  Continuous-Assignment Models  level sensitive behavior module compare_2_CA1 (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0); input A1, A0, B1, B0; output A_lt_B, A_gt_B, A_eq_B; assign A_lt_B = ({A1,A0} < {B1,B0}); assign A_gt_B = ({A1,A0) > {B1,B0}); assign A_eq_B = ({A1,A0} == {B1,B0}); endmodule

43. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Comparator Model (Cont)  Dataflow/RTL Models  edge sensitive behavior module compare_2_RTL (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0); input A1, A0, B1, B0; output reg A_lt_B, A_gt_B, A_eq_B; always@ (A0 or A1 or B0 or B1) begin A_lt_B = ({A1,A0} < {B1,B0}); A_gt_B = ({A1,A0) > {B1,B0}); A_eq_B = ({A1,A0} == {B1,B0}); end endmodule

44. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Comparator Model (Cont)  Algorithm-Based Models module compare_2_algo (A_lt_B, A_gt_B, A_eq_B, A,B); input[1:0] A,B; output reg A_lt_B, A_gt_B, A_eq_B; always@ (A or B) begin //Level-sensitive behavior A_lt_B = 0; A_gt_B = 0; A_eq_B = 0; if (A == B) A_eq_B = 1; else if (A >B) A_gt_B = 1; else A_lt_B = 1; end endmodule

45. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Blocking Assignment module shiftreg_PA (E,A,clk,rst); outputA; inputE; inputclk,rst; regA,B,C,D; always @ (posedge clk or posedge rst) begin if(reset) begin A = 0; B = 0; C = 0; D = 0; end else begin A = B B = C; C = D; D = E; end endmodule *result : A = B

46. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Blocking Assignment (Cont) module shiftreg_PA_rev (E,A,clk,rst); outputA; inputE; inputclk,rst; regA,B,C,D; always @ (posedge clk or posedge rst) begin if(reset) begin A = 0; B = 0; C = 0; D = 0; end else begin D = E C = D; B = C; A = B; end endmodule * result : A = E

47. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Non-blocking Assignment module shiftreg_nb (E,A,clk,rst); outputA; inputE; inputclk,rst; regA,B,C,D; always @ (posedge clk or posedge rst) begin if(reset) begin A <= 0; B <= 0; C <= 0; D <= 0; end else begin A <= B B <= C; C <= D; D <= E; end endmodule *result : A = B

48. Verilog 강의자료 REAL TIME ARCHITECTURE LAB Non-blocking Assignment (Cont) module shiftreg_nb_rev (E,A,clk,rst); outputA; inputE; inputclk,rst; regA,B,C,D; always @ (posedge clk or posedge rst) begin if(reset) begin A <= 0; B <= 0; C <= 0; D <= 0; end else begin D <= E C <= D; B <= C; A <= B; end endmodule *result : A = B

49. Verilog 강의자료 REAL TIME ARCHITECTURE LAB ASM Charts for Behavioral Modeling  ASM Charts: Algorithmic State Machine Charts  eg : flow chart for software design  state box  conditional output  decision box  Decide states  Decision box and conditional output box set by algorithms  ASMD Chart : Algorithmic State Machine and Datapath Chart

50. Verilog 강의자료 REAL TIME ARCHITECTURE LAB 4-Bits Parallel Register module Par_load_reg4 (Data_out, Data_in, laod, clk, rst); input[3:0]Data_in; inputload, clk, rst; output[3:0]Data_out; reg[3:0]Data_out; always @ ( posedge clk or posedge rst) begin if (reset == 1 ) Data_in = 4'b0; else if( load ==1 ) Data_out = Data_in; end endmodule 4-bits parallel register