1. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 1 PID electronics summary electronics (on behalf of PID electronics group)

2. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 2 We have two different systems to design for the PID. For the forward PID (TOF/ DIRC like quartz radiators) For the forward PID (TOF/ DIRC like quartz radiators) 200 Channels (!) 200 Channels (!) Count rate up to ~ MHz per channel worst case. Count rate up to ~ MHz per channel worst case. ~ 10 ps. Analog memories seem the only possible option. Two solutions are under study: G. Warner’s boards are already under test and the Wave Catcher board will be installed on Jerry’s test bench and later on the telescope. ~ 10 ps resolution. Analog memories seem the only possible option. Two solutions are under study: G. Warner’s boards are already under test and the Wave Catcher board will be installed on Jerry’s test bench and later on the telescope. For the Barrel: For the Barrel: ~ 30000 Channels ~ 30000 Channels Time resolution: ~100 ps for the electronics Time resolution: ~100 ps for the electronics Charge measurement foreseen for all the channels. Charge measurement foreseen for all the channels. => both for physics and for timing correction (time walk) Count rate : in worst case up to ~ MHz ( less than in the forward) Count rate : in worst case up to ~ MHz ( less than in the forward)

3. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 3 We want to lead the two different studies in parallel. For the forward PID: the development on analog memories is not “SuperB- dependent “. The R@D will anyhow go on. For the barrel : We already have a 16-channel 100ps TDC in hand. For the barrel : We already have a 16-channel 100ps TDC in hand. It has to be adapted for SuperB It has to be adapted for SuperB There are still discussions about using analog memories for the two systems. Waveform gives both time and charge information which is very powerful and very attractive. Waveform gives both time and charge information which is very powerful and very attractive. Having a single chip for the two system is tempting. Having a single chip for the two system is tempting. The are some important drawbacks with analog memories: In case of a large number of channels like in the barrel (30 000 channels), data has to be processed: on-line feature extraction in FPGA or DSP -> power consumption and cost. In case of a large number of channels like in the barrel (30 000 channels), data has to be processed: on-line feature extraction in FPGA or DSP -> power consumption and cost. Dead time for the readout is relatively long (~ µs ). For high count rates a special architecture inside the chip has to be imagined. Dead time for the readout is relatively long (~ µs ). For high count rates a special architecture inside the chip has to be imagined.

4. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 4 FDIRC tests in CRT T1*T2*S1*Qtz_counter rate ~ 6k/24 hours E muon > 1.6 GeV T1*T2*S1*Qtz_counter rate ~ 6k/24 hours E muon > 1.6 GeV Slot 1 has an old SLAC amplifier; slots 2-7 have new BLAB2 chip electronics. Slot 1 has an old SLAC amplifier; slots 2-7 have new BLAB2 chip electronics. Analog Monitoring BLAB2 electronics Old SLAC amplifier for monitoring purposes Cosmic Ray Telescope (CRT):

5. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 5 Principle of timing with BLAB2 With the initial version of the firmware, we were able to achieve a timing resolution of only  ~1ns, which is not good enough to do the chromatic corrections. With the initial version of the firmware, we were able to achieve a timing resolution of only  ~1ns, which is not good enough to do the chromatic corrections. Coarse & fine time: Time = 1300 ns – (COARSE TIME + FINE TIME) BLAB2: - 17 Channels - 16 Signal channels - 1 Reference channel (records trigger signal) - Each channel - 3072 sampling cells - 6 rows, 512 columns - -Each channel amplification (~40x)

6. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 6 From BLAB2 to BLAB3 G. Varner ParameterBLAB2BLAB3 Samples/channel 6 rows x 512 columns 32768 Number of MaPMT pixels / BLAB2 ASIC 168 BLAB2 waveform sampling speed 2.5 GSa/sec 4 GSa/sec On chip ADC 1 GHz Wilkinson 0.7 GHz Wilkinson ADC resolution 10 bits 10 bits (12 bits recording) ADC conversion time for 10 bits 1  s Number of words / event 32 - 512 Read time for 16 channels (1 BLAB2 chip) / event 16  s 2 - 8  s Sustained readout speed 50 kHz > 30 kHz Trigger latency 12  s 5  s Dynamic range 1mV / 1V BLAB2 chip input impedance 30-80  (adjustable) Current input (TIA) Cross-talk < 0.1% < 0.1% Amplifier analog BW ~ 0.85 GHz ~ 0.5 GHz Amplifier gain (TIA = trans-impedance amp) 40 (2k  TIA) 60 (3k  TIA)

7. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 7 ∆t resolution degraded by a factor of √2 SuperNemo experiment: 2 events will be stamped  ∆t = t2- t1 t1  t2   t =  √ 2 ∆t ∆t = t2- t1 As another solution we propose to design a TDC based on the SNATS developed for SuperNemo experiment TDC: time measured between a Start & a Stop Time Stamper: absolute time measurement

8. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 8 One fine time measurement (high resolution)  DLL One coarse time measurement (range)  N-bit counter SNATS: principle

9. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 9 Technology Process: AMS CMOS 0.35µm Technology Process: AMS CMOS 0.35µm Clock Frequency: 160MHz Clock Frequency: 160MHz Number of cells: 32 (limited by the INL) Number of cells: 32 (limited by the INL) Dynamic Range: 53 bits Dynamic Range: 53 bits 48 clock counter bits 48 clock counter bits 5 interpolator bits 5 interpolator bits  Time coverage: 20 days LSB = 200 ps LSB = 200 ps DNL < 10% of the LSB DNL < 10% of the LSB Channels per chip = 16 Channels per chip = 16 Readout dead time per channel: 400ns => 16 *400 for 16 channels Readout dead time per channel: 400ns => 16 *400 for 16 channels Production: shared run as for Babar. Cost: 67 Euros / chip based on a recent production of ~500 chips. Production: shared run as for Babar. Cost: 67 Euros / chip based on a recent production of ~500 chips. Not “ naturally “ protected against SEL => need of a radiation test of SNATS in beam Not “ naturally “ protected against SEL => need of a radiation test of SNATS in beam SNATS target performance summary

10. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 10 Consumption: 3.3V supply 10mA/DLL + 35mA for the rest For 8 DLLs: 115 mA  P= 380 mW Clock signal: LVDS or single input Frequency: 160MHz Low jitter: a few ps RMS Hit signal : Input level between 1V and 3.3V Trigger on rising edge Readout and control signals: 3.3V CMOS Standard SNATS: Electrical Characteristics

11. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 11 Differential Non Linearity (DNL): Single channel measurement

12. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 12 Transfer function: Single channel measurement Time (ps) Code (LSB) INL (LSB) Time (ps) Integral Non Linearity (  / max): 0.36 / ± 1.3 LSB

13. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 13 Resolution: σ = 71 ps 0 1 1.50.5 -0.5 -1.5 Single channel measurement

14. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 14 SNATS: conclusion Timing characteristics: Bin size (LSB)195.3ps Clock frequency 160 MHz  Dynamic range ~20 days Single pulse mode Dual pulse mode Resolution 70ps RMS 101ps RMS DNL (  / max)0.083 /  0.2 LSB 0.024 /  0.08 LSB INL (  / max)0.36 /  1.3 LSB 0.514 /  1.8 LSB Crosstalk<  1 bin (layout mistake) DNL for single pulse mode is high and must be corrected  next submission in 2010

15. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 15 SNATS: Evolution & Perspectives Stake: high count rate detectors   INL, DNL, resolution … : same requirements.   Increase the input data rate up to the Mhz level per chip.   SNATS: 2.5MHz per channel but ~150 kHz per chip Need to reduce dead time due to readout protocol between ASIC and PGA = 50 ns per 16 bit word

16. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 16 SNATS: Evolution & Perspectives 2 options (among many others …)   Keeping almost the same design and just adding a FIFO at the output.   it increases the input channel rate in burst mode but keeps the average readout rate like the previous version.   The FIFO size is costly.   Keeping the Gray counter inside the ASIC with an output bus width set by user in order to reduce the amount of data to be transferred. The Gray counter is duplicated inside the associated PGA.   The serial output is synchronous to the clock to ensure the matching between the 2 counters.   16 differential output channels @ 80 Mhz (160MHz?).   Max performance   5 DLL bits + 4 Gray bits + start bit = 10b @ 80 Mhz = 8Mhz input rate !   Linked to performance of the readout acquisition   Max performance :   Mhz/channel in burst mode but limited by the size of the FIFO.

17. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 17 A very preliminary 16 channel test board synopsis 64 Channels ? USB2/1 - VME Needs to be linked to local DAQ ?

18. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 18 Next steps a) BLAB2 chip works. We have a pixel-based Cherenkov angle resolution as expected. But the firmware needs some fixes to do a timing resolution at a level of 100-200ps. These fixes will be installed in the CRT in December. b) At that point we start taking data capable of the chromatic corrections. c) One reason we were bitten by the BLAB2 chip problems is that we did not have operating the scanning setup, as this electronics is not compatible with it. Therefore, we are putting some effort to restart the scanning setup. Thould will allow detailed bench tests with MaPMT and detailed waveform analysis. d) Incorporate a new Orsay TDC/ADC electronics in the CRT readout, and the scanning setup as well. e) Need more people here at SLAC, if we want to do all this.

19. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 19 “DIRC-like” TOF detector J.V., http://www.slac.stanford.edu/~jjv/activity/Vavra_Forward_TOF_geometry.pdf, Perugia, June 2009 Hamamatsu MCP-PMT (SL-10) with strips and a protection foil: 1 ASIC/16 channels track  10  m holes - Not all photons are of “equal” quality. Some we want to throw away because they are affected by the chromatic broadening. - We do not want photons to rattle around for too long - This design requires a high gain operation to detect single photons Photon absorbing trap polish track Part of a hexagon: Time-of-Proparation: TOP( ,  c, ) = [L photon path )]/[v g ( )] A direct photon is accepted only if: TOP i measured - TOP i expected < Cut Even 3 photons will do as long as they are “good” photons ~30 cm Calibration: Total contact footprint: : ~1cm  ~ 10 ps: 1cm

20. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 20 Target chip & TOF counter bench tests with the laser Light source: PiLas laser diode Light source: PiLas laser diode Two Photonis MCP-PMTs used in the Fermilab test beam setup. Two Photonis MCP-PMTs used in the Fermilab test beam setup. Low gain of 2-3x10 4. Low gain of 2-3x10 4. Fast detector & fast HPK ~1.5 GHz BW amplifier (gain of 63x). Fast detector & fast HPK ~1.5 GHz BW amplifier (gain of 63x). Target chip sampling speed only ~ 2.5 GSa/s (sampling every 400 ps), with very slow front end (~ 0.25 GHz BW). Target chip sampling speed only ~ 2.5 GSa/s (sampling every 400 ps), with very slow front end (~ 0.25 GHz BW). - This leads to the saturation of the leading edge, and this is the trick. => Therefore the timing becomes easier & spline interpolation more precise TOF 1: TOF 2: TARGET chip developed by G. Varner:

21. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 21 Final result with TARGET chip Set Npe ~ 40 pe per laser pulse (equivalent to beam with 1cm-long quartz radiator). Set Npe ~ 40 pe per laser pulse (equivalent to beam with 1cm-long quartz radiator). Low gain operation as during the Fermilab beam test. Low gain operation as during the Fermilab beam test. A combination of fast detector and fast amplifier & low TARGET chip BW gives equal or better result than a 1 GHz BW Ortec CFD/TAC/ADC electronics !?!?! A combination of fast detector and fast amplifier & low TARGET chip BW gives equal or better result than a 1 GHz BW Ortec CFD/TAC/ADC electronics !?!?! Comparison with the same laser test with the Ortec 1GHz BW CFD/TAC/ADC electronics: Results with the Target chip: (analysis 2b) Diff = TOF1 - TOF2  narrow ~ ~ 19 ps/  2 ~ 13 ps - Laser test with TARGET chip Note:  TTS ~ 120 ps because of the low gain Analysis 2a Analysis 2b

22. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 22 The USB_WaveCatcher prototype board SAM Chip Dual 12-bit ADC 1.5 GHz BW amplifier. µ USB Reference clock: 200MHz => 3.2GS/s 2 analog inputs. DC Coupled. Trigger discriminators Trigger input Pulsers for reflectometry applications Board has to be USB powered => power consumption < 2.5W Trigger output Cyclone FPGA +5V Jack plug This board was first designed for reflectometry applications. This board was first designed for reflectometry applications. At the same time, we got involved in an worldwide picosecond working group. At the same time, we got involved in an worldwide picosecond working group. Analog memories seemed to be perfect candidates for precision measurements … Analog memories seemed to be perfect candidates for precision measurements … => we decided to try to push the board’s performances to their maximum!

23. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 23 The Sampling Matrix Structure: main features

24. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 24 Examples of acquisitions: no off-line correction 75 mV amplitude, 1ns FWHM pulse. 3.2GS/s 2ns FWHM consecutive pulses, separated by 22ns, (300mV & 170mV amplitude). 3.2 GS/s Channel 0 Channel 1 Channel 0 Channel 1 -3dB 530 MHz Bode plot for 300mV pp Sinus The goal of the following study is to measure the board’s capacity to perform the measurement of the time difference between two pulses (like a TDC but directly with analog pulses !). No offline correction except the subtraction of the fixed pedestal distribution No offline correction except the subtraction of the fixed pedestal distribution

25. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 25 Timing measurement with two pulses. Source: asynchronous pulse summed with itself reflected at the end of an open cable. Source: asynchronous pulse summed with itself reflected at the end of an open cable. Time difference between the two pulses extracted by crossing of a fixed threshold determined by polynomial interpolation of the 4 neighboring points (on 3000 events). Time difference between the two pulses extracted by crossing of a fixed threshold determined by polynomial interpolation of the 4 neighboring points (on 3000 events). σ Δt ~ 11ps rms => jitter for a single pulse = 8 ps ! σ = 10.9ps rms σ = 11.4ps rms Δt ~ 11ns Δt ~ 21ns Vth

26. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 26 2 DC-coupled 256-deep channels with 50-Ohm active input impedance ±1.25V dynamic Range, with full range 16-bit individual tunable offsets 2 individual pulse generators for reflectometry applications. On-board charge integration calculation. Bandwidth > 500MHz Signal/noise ratio: 11.9 bits rms (noise = 630 µV RMS) Sampling Frequency: 400MS/s to 3.2GS/s Max consumption on +5V: 0.5A Absolute time precision in a channel (typical): without INL calibration: 20ps rms (400MS/s to 1.6GS/s) 16ps rms (3.2GS/s) after INL calibration 12ps rms (400MS/s to 1.6GS/s) 8ps rms (3.2GS/s) Relative time precision between channels: still to be measured. Trigger source: software, external, internal, threshold on signals Acquisition rate (full events)Up to ~1.5 kHz over 2 full channels Acquisition rate (charge mode)Up to ~40 kHz over 2 channels Summary of the board performances. Acquisition software with graphical interface is under development

27. Christophe Beigbeder - SuperB meeting - SLAC Oct 2009 27 Summary 1. 1.TDC: the SNATS chip seems to be OK for the barrel except its trigger rate capability -> We plan to design a new TDC with a much faster readout. 2 2We need to develop a specific ASIC to measure the PM charge and produce hits for the TDC. We have to find new collaborators on that item. Paris 6 has been contacted … 3 3We plan to develop a test board with the current version of the TDC (SNATS) and with a discrete analog amplifier and discriminator to test on the telescope. 4 4The wave catcher has been mounted on Jerry’s test bench yesterday and it will be adapted to the telescope soon 5 5Studies were performed with Gary Varner’s TARGET chip to see if a 2.5 GSa/s waveform digitizing electronics with 250 MHz of BW can compete with the Ortec electronics. The results were surprisingly good. This has to be studied more thoroughly. 6 6Pixilated TOF detector were tested in the Fermilab test beam with HPK amplifier (1.6 GHz BW) and Ortec 1GHz BW CFD/TDC/TAC.