1. 17 nov 2009 1 FEC4_P2 status P.Pangaud ; S.Godiot ; R.Fei ; JP.Luo Remember : P2 from P1 Optimization of Rad-Hard block and SEU tolerance blocs Optimization of Analogue part vs Chartered Technology But to follow the IBM release FEI4_P1 chip, we kept the same functionalities Reduce the pixel size to 125µmPlan Analog Pixel and analog functions Global register Digital Buffers SEU latch Next … Project can be visited at the FEC4 SOS server Marchips : FEC4

2. 17 nov 2009 2 FEC4 : Pixel overview ( size 50 x 166) FEC4_P1 FEC4_P2 1st SEU LATCH version FEC4_P2 2nd SEU LATCH version From FEI4_P1 : Basically Technology translation from IBM to Chartered Optimization of analog part and a new SEUlatch Optimization of analog part and a second new SEUlatch

3. 17 nov 2009 3 FEC4_P2 : Main changes in analogue pixel The objectives were :  Not to change the structure  Simulate and adjust size of transistors

4. 17 nov 2009 4 Pre-amplifier FEC4-P1 :  MN2 : 3µ/200n, nf=2, nmos_1p5_lvt  T21 : 6,25µ/300n, nf=2, nmos_1p5_nat FEC4-P2 :  MN2 : 5,5µ/300n, nf=1, nmos_1p5_nat  T21 : 5,5µ/300n, nf=2, nmos_1p5_nat  For Process variation : Better behavior with the same kind of transistor…

5. 17 nov 2009 5 Amplifier2 To deal with increased Vt and to improve the linearity : Nf = 4 To increase the linearity : Bulk and source connected only 1 transistor (not 2 in series) with the same equivalent size

6. 17 nov 2009 6 Simulation results typical process linearity : Noise from 60 e- to 200 e- depending on :  the process case  the capacitor value of the sensor (from 0 to 400fF)  The sensor current (from 0 to 100nA) All results will be presented in a forthcoming document ampli2 preampliampli2 preampli

7. 17 nov 2009 7 Global Register Due to a defect working after irradiation, we decided to replace the SEU_LATCH cell by a LATCH Standard Cell from ARM.

8. 17 nov 2009 8 Global register cell Arm latch Port definition G : Load signal, the latch hold signal from DFF while the load signal is”0”. SN : Connect with a TIETHL. So the state always is “1”. RN : Clear signal. Connect it with an ‘Not gate’. So the ltchclr is high positive. D : Connect with DFF’s output ‘Q’. Q : The output of latch. Follow by a buffer. QN : Not used. Functions: RNSNGDQ[n+1]QN[n+1] 111001 111110 110XQ[n]QN[n] 01XX01 10XX10 00xX10

9. 17 nov 2009 9 Layout 49.1u*82.3u of FEC4_P1 per 16 cell 49u*82.3u of FEC4_P2 per 16 cell

10. 17 nov 2009 10 Modification of Digital Buffers

11. 17 nov 2009 11 Fist stage, N: 0.44/0.14 P: 1.25/0.14 Second stage, N: 4.5/0.14 P: 13.5/0.14

12. 17 nov 2009 12 Fist stage, N: 4.625/0.13 P: 12/0.13 Second stage, N: 13.875/0.13 P: 36/0.13 Wellguardring for PMOS Enclosed Layout Transistor Guardring for NMOS

13. 17 nov 2009 13 Frequency of the input signal: 1/20ns (50MHz). Mode transistors: typical. Load capa = 10p. P1 P2 rise time: 4,494ns fall time: 5,341ns rise time: 1.786ns, fall time: 1.657ns

14. 17 nov 2009 14 20psftypicalfs rise time3,1133,5284,074 fall time3,7753,2652,894 25p rise time3,8464,4015,083 fall time4,7334,1033,591

15. 17 nov 2009 15 SEU Latch in Pixel cell Some ideas…  Optimization of the SEU Latch block  New layout  With and without ELT  Try the Triple Nwell But only new layout and with and without ELT have been implemented

16. 17 nov 2009 16 SEU_LATCH (DICE) version 1 Added buffers at the inputs and outputs and load. Removed the Reset function. Linear Transistors used + guardring All corners simulation are OK

17. 17 nov 2009 17 SEU_LATCH (DICE) version 2 Added buffers at the inputs and outputs and load. Removed the Reset function. Replaced the Load switch by a Tgate ELT Transistors used + guardring All corners simulation are OK

18. 17 nov 2009 18 SEU_LATCH (DICE) version 3 Added buffers at the inputs and outputs and load. Removed the Reset function. Add Triple well and removed the Dual function ELT Transistors used + guardring Very bigger cell Not implemented. Not enough time ….. But very exiting approach

19. 17 nov 2009 19 Other changes Current mirrors at the output of global DAC : L is increased (for a small improvement of matching and noise) (for example 1µ/1µ becomes 1µ/4µ…) Analogue buffers : → Not enough time to design a real output buffer. → Layout is drawn with enclosed NMOS. Layout correction For FEC4-P1, suba, subd, gnda and gndd are not correctly separated. → This is corrected for P2. PADs ring : new approach (the same used for FETC4) → suba and subd are separated from gnd and sub of ESD protection. → use of dedicated PADs for VDDAIO, VDDDIO and GNDAIO, GNDDIO (PADs power).

20. 17 nov 2009 20 Conclusion …. Optimization of design : OK Repaired Test transitors : OK Checked the ESD Pads : OK Reduced the pixel size : NOK Added a real analog buffer : NOK We are preparing a Design document of the FEC4_P2 chip + test description (and Pinout)