1. Data Converter Performance Metric EE174 – SJSU Tan Nguyen

3. Analog-to-Digital Converter (ADC)

4. ADC: Ideal Transfer Function and Quantization Error For an ideal ADC: Quantization error is bounded by –Q/2 … +Q/2 for inputs within full-scale range If the ADC is ideal, the steps shown are perfectly superimposed on a line.

5. Dynamic range is a term used to describe the ratio between the smallest and largest signals that can be measured by a system. The dynamic range of a data acquisition system is defined as the ratio between the minimum and maximum amplitudes that a data acquisition system can capture. For a 16-bit device the total voltage range is represented by 2 16 = 65536 discrete digital values. Therefore the absolute minimum level that a system can measure is represented by 1 bit or 1/65536 th of the ADC voltage range. In decibels this dynamic range is therefore expressed as: 20 Log 10 (65536) = 96dB Therefore for a 16-bit ADC the dynamic range is 96dB. Using the same calculations the dynamic range of a 24-bit ADC is 144dB. ADC Dynamic Range

6. Signal to Quantization Noise Ratio Under certain conditions the quantization error can be viewed as "random", and is often referred to as “noise” In this case, we can define a maximum “signal-to-quantization noise ratio”, SQNR, for sinusoidal inputs: Real converters do not quite achieve this performance due to other sources of error: – Electronic noise – Deviations from the ideal quantization levels

7. The theoretical ideal transfer function for a DAC is also a straight line with an infinite number of steps but practically it is a server of points that fall on the ideal straight line as shown in Figure 2. A DAC represents a limited number of discrete digital input codes by a corresponding number of discrete analog output values. Therefore, the transfer function of a DAC is a series of discrete points as shown in Figure 2. For a DAC, 1 LSB corresponds to the height of a step between successive analog outputs, with the value defined in the same way as for the ADC. A DAC can be thought of as a digitally controlled potentiometer whose output is a fraction of the full scale analog voltage determined by the digital input code. Digital-to-Analog Converter (DAC)

8. Ideal Transfer Function DAC DAC: Ideal Transfer Function Ideal DAC introduces no error! One-to-one mapping from input to output

9. Data Converter Performance Metrics Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : Static Offset Full-scale error Differential nonlinearity (DNL) Integral nonlinearity (INL) Monotonicity Dynamic Delay & settling time Aperture uncertainty Distortion-harmonic content Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR) Idle channel noise Dynamic range & spurious-free dynamic range (SFDR)

10. Static Errors on Converters

11. Offset Error (Zao scale er) The offset (or zero-scale) error is defined as the difference between the nominal and actual offset points and measured in LSBs. Offset Errors: ADC and DAC For an ideal ADC, the first transition occurs at 0.5LSB above zero. For an ADC, the offset voltage is applied to the analog input and is increased until the first transition occurs. ADC offset error can be removed be measuring a reference point and subtracting that value from future samples. For a DAC, offset error is the analog output response to an input code of all zeros. 0.5 2.5LSB

12. Gain Error Gain Errors: ADC and DAC The gain error of an ADC or DAC indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function after the offset error has been calibrated out. Gain error is usually expressed in LSB or as a percent of full-scale range (%FSR), and it can be calibrated out with hardware or in software.

13. Diffal DNL) Error DNL of ADC & DAC 7 6 5 4 3 2 1 k = 0 For a DAC, DNL error is the difference between the ideal and the measured output responses for successive DAC codes. An ideal DAC response would have analog output values exactly 1LSB apart (DNL = 0). DNL specs ≥ 1LSB guarantees monotonicity in DAC 7 6 5 4 3 2 1 V out = 0 + 1.0

14. Fig. 1: Wide code width Fig. 2: Missing code Fig. 3: Narrow code width Fig. 4: Non-monotonic ADC DNL Error Fig. 1: The 0x800 code width is 2 LSB (Wide code width).  DNL = +1 LSB. Fig. 2: 0x800 code width is 0 LSB (Missing code).  DNL = – 1 LSB. Since 0x800 is missing, the ADC cannot be used for high precision applications. Fig. 3: The 0x800 code width is 0.25 LSB (Narrow code width).  DNL = – 0.75 LSB, Since the 0x800 is still there, the ADC can be used in precision applications. In Fig. 4: The 0x800 code width is – 0.25 LSB (undefined/non- monotonic).  DNL = – 1.25 LSB. It is clear that the ADC is highly nonlinear.

15. Non-Monotonic DAC

16. ADC Integral Nonlinearity (INL) End-point Best fit

17. DAC Integral Nonlinearity (INL) Can derive INL by: Connect end points Find ideal output values INL for each code: INL is found by computing the cumulative sum of DNL m – 1 INL(m) = ∑ DNL[i] i = 1

18. The INL error is the deviation of the values on the actual transfer function from a ideal straight line. This straight line can be either a best straight line which is drawn so as to minimize these deviations or it can be a line drawn between the end points of the transfer function once the gain and offset errors have been nullified. The second method is called end-point linearity and is the usual definition adopted since it can be verified more directly. For an ADC the deviations are measured at the transitions from one step to the next, and for the DAC they are measured at each step. INL is often called 'relative accuracy.' INL of ADC & DAC

19. Transition # Ideal transition point Real transition point Code width [V] Width [LSB]DNL=W - 1INL = ∑ DNL 10.050.020.131.180.180 20.15 0.050.45-0.550.18 30.250.20.171.550.55-0.37 40.350.370.050.45-0.550.18 50.450.420.080.73-0.27-0.37 60.550.50.181.640.64-0.64 70.650.68***0 ADC Offset, Gain, DNL and INL Example

20. ADC Differential & Integral Nonlinearity Example Notice: For end-point corrected measurement INL[0]  undefined INL[1]=0 INL[2 N -1]=0 k INL (k) = ∑ DNL[i] i = 1

22. Total Unadjusted Error (TUE) The Total Unadjusted Error (TUE) specification is an indication of the ADC’s worst rms error without applying any Offset or Gain Error correction. The TUE number is not calculated as a summation of Offset, Gain, DNL and INL errors. Since it is an RMS number, the TUE is calculated as TUE = sqrt (sq(Offset Error) + sq(Gain Error) + sq(DNL) + sq(INL)) It is important to convert all the errors to same units. For example, ADC with Offset Error = 3 LSB, Gain Error = 4 LSB, DNL = 1 LSB and INL = 2 LSB, will have TUE = sqrt (9 + 16 + 1 + 4) and TUE = 5.48 LSB Since the offset and gain error can be calibrated out from the ADC transfer curve, the actual error in the application will be dominated by INL and DNL errors.

23. Conversion Between Units Percentage to dB – dB = 20 × log ( Percentage / 100) – that is, 1% = –40 dB and 0.1% = –60 dB dB to V rms – Assuming input amplitude as 1 V rms and for 60 dB SNR, – Noise Amplitude is dB = 20 × log (Input Amplitude / Noise Amplitude) – Noise Amplitude V rms = 0.001, that is, 1 mV rms – If the spec is –60 dB, then the formula will be dB = 20 × log (Noise Amplitude / Input Amplitude)

24. Offset Error Example Offset Error value is usually specified using one of the following units: Volts, Least Significant Bits (LSB), %Full Scale Value (%FSV), and parts per million (ppm). For the above example, you can convert between different units as shown in the following example. Calculate a 3 LSB offset error conversion to Volts: Offset Error (V) = Error in LSB × Maximum Input / (2 N ) Offset Error (V) = 3 × 5 V / (2 16 )  FSV = 5V, N=16 Offset Error (V) = 0.000229, that is, 229 μV spacer Offset Error (%FSV) = Offset Error (V) × 100 / Full scale value Offset Error (%FSV) = 0.00458% in term of ppm, with regard to full scale voltage, is Offset Error (ppm FSV) = 46 ppm Though the offset error is usually specified at 25°C in the data sheets, the offset does vary with temperature. The variation in offset is specified as Offset Drift and denoted as ppm/°C. The actual offset at any temperature can be calculated by adding the drift to offset value calculated for room temperature. For the above example if the drift is specified as 1 ppm/°C of REF V. Offset at 85°C = 229 μV + [(85 – 25) × 5 μV] = 529 μV.

25. Gain Error Example For the above ADC, if the gain error is 4 LSB, then it can be converted to Volts as follows: Gain Error (Volts) = Error in LSB × Maximum Input / (2 N ) Gain Error (Volts) = 4 × 5 / (2 16 ) = 0.000305 V, that is, 305 μV This means the ADC will reach 0xFFFF code for input voltage of 4.999656 V. If the gain error is –4 LSB, then the device will reach 0xFFFF code for input voltage 5.000267 V. Gain Error (%FSV) = Gain Error (V) × 100 / Full scale value Gain Error (%FSV) = 0.0061% Similar to offset error, the gain error is usually specified at 25°C in the data sheets and the gain also varies with temperature. The variation in gain is specified as Gain Drift and denoted as ppm/°C. The actual gain error at any temperature can be calculated by adding the drift to gain error value calculated for room temperature. For the above example, if the drift is specified as 1 ppm/°C of REF V. Gain Error at 85°C = 305 μV + [(85 – 25) × 5 μV] = 605 μV.

26. The following slides is for Reference Only

27. AC (or Dynamic) Errors An ADC's performance has different important specifications when the input varies quickly. These different parameters which define the ADC performance with Dynamic input are mostly specified using single input frequency. The ADC output array is processed using FFT and analyzed for dynamic specifications. Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-Noise and Distortion (SINAD) Spurious Free Dynamic Range (SFDR) Conversion Between Units

28. Total Harmonic Distortion (THD) The Total Harmonic Distortion (THD) specification provides information regarding the harmonic energy present in the frequency spectrum for a particular input frequency. The frequency spectrum is typically shown till the Nyquist frequency and the THD calculation usually takes into account all the harmonics energy till Nyquist. Harmonics beyond Nyquist fall back into the frequency spectrum as noise or spurious tone. These are taken care of in the SNR and SINAD specifications. The parameter is usually specified in terms of dB or %. THD = Summation of harmonic energy / Fundamental input energy

29. Signal-to-Noise Ratio (SNR) The Signal-to-Noise Ratio (SNR) specification provides information regarding the noise energy excluding the fundamental and harmonic energy present in the frequency spectrum for a particular input frequency. The SNR calculation usually integrates noise till Nyquist frequency. If not, the specifications will imply the band of frequency where the noise is integrated. The parameter is usually specified in terms of dB, V rms, or %. SNR = Fundamental input energy / Summation of noise energy

30. Signal-to-Noise and Distortion (SINAD ) The Signal-to-Noise and Distortion (SINAD) specification provides information regarding the noise and harmonic energy present in the frequency spectrum. The parameter is usually specified in terms of dB, V rms, or %. SINAD = Fundamental input energy / Summation of noise + distortion energy Spurious Free Dynamic Range (SFDR) The Spurious Free Dynamic Range (SFDR) specification provides information regarding the difference between maximum amplitude tone in frequency spectrum and the fundamental input tone. The parameter is usually defined in dB. SFDR = Fundamental input energy – Max (all frequency bins except fundamental)

31. SFDR Measurement

32. THE MATHEMATICAL RELATIONSHIPS BETWEEN SINAD, SNR AND THD There is a mathematical relationship between SINAD, SNR, and THD (assuming all are measured with the same input signal amplitude and frequency. In the following equations, SNR, THD, and SINAD are expressed in dB, and are derived from the actual numerical ratios S/N, S/D, and S/(N+D) as shown below:

33. High Speed DAC Performance The ac specifications in evaluating high speed DACs: Settling time Glitch impulse area Distortion Spurious free dynamic range (SFDR) Signal-to-noise ratio (SNR)

34. DAC SETTLING TIME – Full-Scale Full-scale settling time is the amount of time required for the output to settle with the specified error band measured with respect to the 50% point of either the data strobe to the DAC (if it has a parallel register driving the DAC switches) or the time when the input data to the switches changes (if there is no internal register). The error band is usually defined in terms of an LSB or % full-scale.

35. DAC SETTLING TIME Mid-Scale Mid-scale settling time is also of interest, because in a binary-weighted DAC, the transition between the 0111…1 code and the 1000…0 code produces the largest transient. In fact, if there is significant bit skew, the transient amplitude can approach full-scale.

36. GLITCH IMPULSE AREA Ideally, when a DAC output changes it should move from one value to its new one monotonically. In practice, the output is likely to overshoot, undershoot, or both. This uncontrolled movement of the DAC output during a transition is known as a glitch.

37. References: www.ti.com/lit/an/slaa587/slaa587.pdf 1. Understanding Data Converters – SLAA013 2. ADS8318 data sheet – SLAS568A http://masteringelectronicsdesign.com/an-adc-and-dac-least-significant-bit-lsb/ http://www.analog.com/static/imported-files/tutorials/MT-003.pdf https://inst.eecs.berkeley.edu/~ee247/fa07/files07/lectures/L12_f07.pdf http://www.hit.bme.hu/~papay/edu/Acrobat/DataConv.pdf http://masteringelectronicsdesign.com/an-adc-and-dac-integral-non-linearity-inl/ Evaluating High Speed DAC Performance by Walt Kester – Analog Devices MT-013 Tutorial https://inst.eecs.berkeley.edu/~ee247/fa07/lectures.html http://www.dspguide.com/ch3/1.htm http://www.cse.psu.edu/~chip/course/analog/lecture/SFDR1.pdf http://www.cypress.com/file/144536/download http://www.atx7006.com/articles/static_analysis/dac#gain_error https://www.maximintegrated.com/en/app-notes/index.mvp/id/641 http://blog.prosig.com/2008/04/14/what-is-db-noise-floor-dynamic-range/