Ivan Peric, 2nd CHIPP Workshop on Detector R&D 1 High-Voltage CMOS Technology Ivan Peric University of Heidelberg, Germany.

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 1 High-Voltage CMOS Technology Ivan Peric University of Heidelberg, Germany

Ivan Peric, 2nd CHIPP Workshop on Detector R&D HVCMOS detectors 2 HV CMOS detectors are depleted active pixel detectors Main charge collection mechanism is drift Implemented in commercial CMOS (HV) technologies (350nm, 180nm, 65nm) PMOSNMOS p-substrate Depletion zone Potential energy (e-) deep n-well Drift Diffusion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D HVCMOS detectors 3 Collection electrode is a deep-n-well in a p-substrate Pixel electronics is embedded in the n-well (PMOS: directly, NMOS in a p-well) Can be implemented in various commercial technologies The possibility to bias the n-well with a high voltage improves the characteristics Best properties offer HV CMOS technologies – the n-well is deep enough so that reverse voltages of up to ~100V can be used (no punch through between p-well and substrate) Avalanche multiplication above ~80V p-substrate Depletion zone Potential energy (e-) deep n-well Drift Diffusion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal 4 Example for AMS: 20/10  cm (350/180nm CMOS) substrate resistance -> acceptor density ~ 10 15 cm -3 Depleted layer thickness estimation from the technology datasheet (area capacitance) for 60V bias (~100 max): 10µm (350nm), 7µm (180nm) Typical measured MIP signal for a 50 µm x 50 µm pixel in AMS 0.35 µm (60V bias): 1800e We estimate (10µm thickness) about 800e from depleted region and about 1000e additionally (diffusion or drift in weak field) p-substrate Depletion zone Potential energy (e-) deep n-well Drift Diffusion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal 5 Testbeam results in 350nm technology: Estimation ~800 e from drift (21µm x 21µm pixel) Cluster signal ~ 2200 e Seed: drift+ diffusion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal 6 Results obtained with a detector in 180nm – 33µm x 125µm pixels Measured Sr-90 MPW signal at 50V bias voltage ~1600e “Diffusion” part estimated by fit ~ 820 e, drift 780e

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 7 Collection time measurement Comparison of the response delay to capacitive test pulse (delay only caused by the amplifier) and the delay to IR pulse (delay caused by the amplifier and collection time). To assure that amplifier delay is equal, we equalize the signal amplitudes for both injections. The amplitudes are measured as ToT. Test signal Ampl. out Comp out IR laser signal Ampl. out Comp out del2 1400e N-well 5µ m 10µ m 60% drift ToT is proportional to the input charge. It does not depend on the amplifier rise times. Absorption of 850nm light ~14µm Similar spatial distribution of the charge generation as for MIPs Depleted (drift) 40% diffusion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 8 Collection time measurement Charge collection time – IR laser, comparison with the fast capacitive injection. No measurable delay versus the capacitive test pulse. Ampl. out Comp out

Ivan Peric, 2nd CHIPP Workshop on Detector R&D General development 9 Two development periods: 1) general development and 2) applications In phase 1) we used (mostly) AMS 0.35µm technology Several prototypes have been designed Three detector types: A) Monolithic detector with intelligent CMOS pixels Pixel electronic is rather complex – CMOS based charge sensitive amplifier, usually discriminator, threshold tune… B) Monolithic detector with 4-PMOS-transistor pixel and rolling shutter RO C) Capacitively coupled hybrid detectors Good results, >98% efficiency in test-beam, high radiation tolerance

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Charge integrating pixel detector HVPixelM chip: 21x21 µm pixel size 128 x 128 pixel matrix Res Sel 3.3 V Sensor diode Reset V. Out 10

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Test-beam results: HVPixelM Efficiency at TB: ~98% (probably due to rolling shutter effects – one row out of 64 is in reset state. Seed pixel SNR 27, seed signal 1200e, cluster 2000e Spatial resolution 3-3.8µm 11

Ivan Peric, 2nd CHIPP Workshop on Detector R&D HVPixel - a pixel with CMOS-based electronics 40 µm 12

Ivan Peric, 2nd CHIPP Workshop on Detector R&D HVPixel - a pixel with CMOS-based electronics Left: Response probability of the entire pixel matrix for 660e test pulse and the noise occupancy. Right: MIP spectrum measured at SPS (CERN). 13

Ivan Peric, 2nd CHIPP Workshop on Detector R&D SDS – the detector in 65nm technology - 2.5 µm pixels Res Sel 1.1 V Sensor diode 1.1 V Reset V. Out 2.5 µm 14

Ivan Peric, 2nd CHIPP Workshop on Detector R&D SDS – the detector in 65nm technology - 2.5 µm pixels 55Fe measurement Shadow of 16  m thick golden bonding wire ~16µm Pixel matrix (32x256) 15

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Properties of HVCMOS Detectors 16 Good properties: Fast charge collection (field ~ 6-8.5V/µm, collection time ~ 200ps) High radiation tolerance Thinning is possible (active region several 10µm at the surface) Relatively cheap due to the use of a commercial process (1.5 kEUR / 8inch wafer) Disadvantages: Small depleted region, relatively small (compared to fully depleted sensors) primary- (drift collected) signal, pixel capacitance ~100fF for larger pixels SNR can be improved using the charge sensitive amplifier at the cost of increased power Main challenges: achieve good detection efficiency and low time walk for a given power budget Simulation example for 30µm x 125µm pixel: a good SNR and a time walk of about 10ns can be achieved at the power consumption of about 100mW/cm 2 Some limitations arise from the fact that the electronic is placed inside the collecting electrode Additional capacitance, crosstalk Solution: the use of simplified pixel electronics

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Planned applications 17 Mu3e and PANDA (GSI) HLLHC e.g. ATLAS CLIC

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Development for Mu3e Detector 18 180nm HVCMOS technology chosen due to lower power consumption Low particle energy, thin detector required => monolithic pixel detector, thinned to 50µm Pixels contain only CSAs, every pixel connected to its readout cell, placed at the chip periphery, by an individual wire The concept is feasible for large pixels (80µm x 80µm) Advantages: minimal pixel capacitance, optimal SNR, separation of digital and analog circuits Disadvantage: inactive periphery (about 5%) Readout cells

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Mu3e Detector 19 Readout cells

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Sensor pixel A LP R Amplifier 20

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Pixel readout cell D 4-bit DAC (CR filter) In RW Comparator BL Th TS Memory S R S RPriority Address LdRead Rd TSTSoutRAMout Wr In x n x HitIn HitOut 21 x +n Wr Rd

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Column readout cell S RPriority ColAddr LdRead Rd Wr x n x HitIn HitOut 22 xx RdPixHitOutPix PD Rd RdPix TS/RowAddr

Ivan Peric, 2nd CHIPP Workshop on Detector R&D MuPixel 23 92µm

Ivan Peric, 2nd CHIPP Workshop on Detector R&D MuPixel 24 92µm

Ivan Peric, 2nd CHIPP Workshop on Detector R&D MuPixel – readout cell 25 TS DRAM Address ROM CMOS digital part Comparator Coupling capacitor DAC and SRAM

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Readout 26 LdPix LdCol RdCol

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Readout 30 LdCol RdCol LdPix

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Readout 34 RdCol LdPix LdCol

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Readout 36 RdCol LdPix LdCol Hit

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Readout 38 RdCol LdPix LdCol Hit Add/Ts

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Readout 49 LdPix LdCol Hit RdCol

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Noise measurement 54

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Fe-55 spectrum 55

Ivan Peric, 2nd CHIPP Workshop on Detector R&D X-ray image 56

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Development for HLLHC (ATLAS) 57 Concept: The use of active HVCMOS sensors as replacement for the standard strip- and pixel- sensors and the use of existing (or slightly modified) readout ASICs Group of pixels connected to one readout channel, address information is coded as signal amplitude Realization: one pixel contains: CSA, comparator, threshold tune circuit and the address generator Address signals of the grouped-pixels are transmitted to the input of the RO-channel ROC A

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Pixel Readout 58 Pixel readout: three pixels connected to one readout channel of the ATLAS FEI-chip (FEI4) Capacitive sensor-to-chip signal transmission, no need for bump bonds Advantages: smaller pixels, different pixel geometries can be combined with one ASIC (e.g. for the end caps), little material, fast readout, good resolution for large incident angles Glue Pixel readout chip (FE-chip) Pixel CMOS sensor 33x 125 μm Summing line Transmitting plate Pixel electronics based on CSA Bump-bond pad Coupling capacitance

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Strip Readout 59 Strip readout: larger number of pixels (e.g. 100) grouped into segmented strips, readout with an amplitude sensitive strip-readout chip (multichannel chip) Advantages: Pixel detector (nxn pixels) is readout with a relatively small number of analog channels (~n) – in contrast to rolling shutter readout, time resolution is high Less material than in the case of the hybrid pixel detector and a similar time resolution. If summing scheme can cope with two simultaneous hits, the concept can work at relatively high occupancies (e.g. 8 particles / cm 2 / 25ns ) Summing line Every pixel generates unique current

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Experimental Results 60 Results of the project A small detector prototype chip “CCPD” has been designed (rad-soft and rad-hard version) CCPD can be readout with both a strip- and a pixel-readout chip Stand-alone readout is also possible 2 3 1 2 3 1 CCPD Pixels

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Experimental Results 61 Results of the project A small detector prototype chip “CCPD” has been designed (rad-soft and rad-hard version) CCPD can be readout with both a strip- and a pixel-readout chip Stand-alone readout is also possible

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Experimental Results 62 Tests with pixel readout chip (it works - three addresses can be distinguished, first testbeam measurement done, time stamp distribution ok => good time resolution) 2 3 1 2 3 1 CCPD Pixels Signal amplitudes measured by FEI4

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Noise and Threshold Dispersion 63 Threshold and injection scans – noise, threshold dispersion Results for CCPD2 optimized for radiation hardness (not for low noise) Average pixel noise ~ 75e (large spread) Threshold tuning: dispersion ~ 25e Estimated MIP signal at 50V: 1600e Noise distribution Threshold dispersion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Irradiations – CCPD1 64 1) Two sets of detectors have been irradiated to 435 Mrad and 80 Mrad with protons at the PS (CERN) (chips on during irradiation) 2) X-ray irradiation to 50 Mrad (chips on during irradiation) 3) Neutron irradiation to 10 16 neq/cm 2 (chips off during irradiation, only nonionizing damage) Influence of ionizing radiation higher than expected. Despite of that, Sr-90 spectrum can be measured after 80Mrad (proton irradiation) CCPD1 irradiated to 80 Mrad with protons Sr-90 spectrum CCPD1 at 380 Mrad (810 15 n eq ) proton-irradiation Beam signals

Ivan Peric, 2nd CHIPP Workshop on Detector R&D CCPD2: X-Ray Irradiation to 862 Mrad 65 Several weak points in design have been identified that cause CCPD1 to be susceptible to ionizing radiation (symptoms are: gain drop and base line shift) The weak pints have been fixed in CCPD2 (at expense of a slightly higher noise) CCPD2 implements three pixel types, fully rad hard, partially rad hard and a simple pixel that uses positive feedback and has a CMOS comparator A detector has been irradiated to 862 Mrad with x-rays. (chips on during the irradiation, 2 hours of annealing at 70C after each 100Mrad) Result for one partially rad hard pixel: input referred noise before irradiation 25mV (90 e) Input referred noise after irradiation 40mV (150 e) at room temperature We observe that amplifiers work with reduced bias current (2µA instead of 5µA) – probably only partially rad hard pixels are affected – bias NMOS diode can be affected by oxide charge 862 Mrad 90e150e

Ivan Peric, 2nd CHIPP Workshop on Detector R&D CCPD2: X-Ray Irradiation to 862 Mrad 66 The radiation hardening measures done for CCPD2 seem to be successful CCPD1 irradiated with x-rays Amplifier gain loss CCPD2 irradiated with x-rays Amplifier gain loss Rad hard pixels Re-optimization of the settings Dose 862 Mrad

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Segmented Strip Measurements 67 Setup

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Segmented Strip Measurements 68 Strip measurement circuit Amp Monitor Chip Oscilloscope Th1 Fe55 Absorber

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Conclusion and Outlook 71 HVCMOS detectors are depleted monolithic detectors Good time resolution, high radiation tolerance, little material, low cost Planned applications: Mu3e, HLLHC and CLIC Results: Signal and noise should allow a good detection efficiency Detectors work after 10 16 n eq /cm 2 and 860 Mrad – efficiency should still to be measured Time resolution seems ok Synergy between projects: engineering run planned in 2014

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 72 Thank you!

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 73 Backup Slides

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 74 Collection time measurement Comparison of the response delay to capacitive test pulse (delay only caused by the amplifier) and the delay to IR pulse (delay caused by the amplifier and collection time). To assure that amplifier delay is equal, we equalize the signal amplitudes for both injections. The amplitudes are measured as ToT. Test signal Ampl. out Comp out IR laser signal Ampl. out Comp out del2 1400e N-well 5µ m 10µ m 60% drift ToT is proportional to the input charge. It does not depend on the amplifier rise times. Absorption of 850nm light ~14µm Similar spatial distribution of the charge generation as for MIPs Depleted (drift) 40% diffusion

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 75 Collection time measurement Charge collection time – IR laser, comparison with the fast capacitive injection. No measurable delay versus the capacitive test pulse.

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Mu3e Detektor Scintillator tiles Recurl pixel layersOuter pixel layers Inner pixel layers Scintillating fibres Vier Pixellagen ~ 80x80  m 2 Pixel Zeitauflösung: 100ns Dünne Sensoren: ~50  m Kühlung mit Helium Fläche: 1.9 m 2 275 M Pixel Heidelberg, PSI, Zürich, Genf

Ivan Peric, 2nd CHIPP Workshop on Detector R&D PANDA Luminositätsmonitor Luminosität wird anhand der Winkelverteilung der elastisch gestreuten Antiprotonen bei sehr kleinen Winkeln extrahiert Vier Ebenen Das gesamte Detektorsystem befinden sich im Vakuum um Vielfachstreuung zu minimieren Um die Materialbelegung gering zu halten, werden die Sensoren auf 200 µm dünnen Diamantscheiben aufgebracht, die an einem Aluminiumträger befestigt sind

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Particle hit N-well e-h 80

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Charge collection Assume: V sat = 8 x 10 4 m/s T col = 188 ps e- 188 ps 81

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Voltage drop in the n-well   Cdet Q/Cdet 188 ps Q 82

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Amplification   Cdet Q/Cdet 188 ps50ns  Q 83

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Feedback action through Cf N-well potential temporary restored Meta-stabile state Cdet Q/Cf  Q 188 ps50ns Q Cf 84

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Reset of the charge sensitive amplifier Cdet Q/Cf  Q 188 ps50ns Q Cf 85

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Reset of the charge sensitive amplifier accomplished: N-well again negative! Cdet 188 ps50ns500ns Q Cc  Cdet Q ~Q/Cdet Assumption: Cc= Cdet 86

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Signal-generation and amplification Initial voltage across the n-well and the coupling capacitance restored by R bias 188 ps50ns500ns>>500ns Rbias 87

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Irradiations – older Results 88 Irradiation studies: Two damage mechanisms: nonionizing and ionizing Results are generally promising, but we still do not have the results from a test-beam measurement with irradiated devices Older results (AMS 0.35µm technology) X-ray irradiation up to 60 Mrad (rad-hard device layout – enclosed transistors, chip on during irradiation) – increased noise and leakage current observed - after annealing and cooling they return to normal noise

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Irradiations – older Results 89 Older results: Proton irradiation to 10 15 neq/cm 2 (standard device layout, chip off during irradiation) – increased leakage and noise – the MIP signal does not decrease significantly – diffusion still works? Neutron irradiation to 10 14 neq/cm 2 (rolling shutter chip) – increased leakage and noise – diffusion part of the signal is decreased Irradiated Not irradiated Proton irradiation at KIT, Karlsruhe Neutron irradiation at Research Reactor Munich

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Standard CCPD Sensor pixels Readout pixels Chip A Chip B Signal transmission wire bonds chips Monolithic matrixCCPD matrix (sensor) CCPD matrix (readout) Electrodes Standard CCPD 55x70 µm pixel size 90

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Standard CCPD Monolithic matrixCCPD matrix (sensor) CCPD matrix (readout) Standard CCPD 55x70 µm pixel size Pixel matrix efficiency: Detection of signals > 1000e possible MIP signal ~ 1800 e 91

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Edgeless CCPD CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size Pixel matrix efficiency: Detection of signals > 350e possible MIP signal ~ 1800 e 92

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Edgeless CCPD Smart diode- or fully-depleted sensor Readout chip Pixel Bump for power supply Signal charge 93

Ivan Peric, 2nd CHIPP Workshop on Detector R&D Tezzaron-GF 3D Process 94 Tezzaron Global Foundries process, offered by Mosis and CMP. Two tier process based on Global Foundries 130nm technologies. Two wafers (tier 1 and tier 2) are connected face to face with Cu-Cu thermo-compression bonding. For this purpose Tezzaron uses the 1µm thick Cu TopMetal to create the “leopard skin” pattern. The Super contacts (TSVs) are realized after the transistor processing and before the metallization – via middle process (TSV diameter of 1,2 µm, TSV distance 25 µm). The top wafer is thinned to access the super contacts. Back side metal is added for bonding after thinning. One tier Bond interface layoutWafer to wafer bonding

Ivan Peric, 2nd CHIPP Workshop on Detector R&D SDA 3D HVCMOS in Tezzaron-GF Process 95 TSV Tier 2 Tier 1 (thinned wafer) Back Side Metal M5 M4 M3 M2 M1 M2 M3 M4 M5 M4 M3 M2 M1 M2 M3 M4 M5

Ivan Peric, 2nd CHIPP Workshop on Detector R&D 1 High-Voltage CMOS Technology Ivan Peric University of Heidelberg, Germany.

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Ivan Peric, 2nd CHIPP Workshop on Detector R&D 1 High-Voltage CMOS Technology Ivan Peric University of Heidelberg, Germany.

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