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TCAD Simulation for SOI Pixel Detectors October 31, 2006 Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec. Ind. Co.), Masashi Hazumi (KEK) for the SOIPIX.

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Presentation on theme: "TCAD Simulation for SOI Pixel Detectors October 31, 2006 Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec. Ind. Co.), Masashi Hazumi (KEK) for the SOIPIX."— Presentation transcript:

1 TCAD Simulation for SOI Pixel Detectors October 31, 2006 Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec. Ind. Co.), Masashi Hazumi (KEK) for the SOIPIX group

2 2006/10/31M. Hazumi (KEK)2 Financial Support by KEK Detector Technology Project SOIPIX collaborators KEK Detector Technology Project : [SOIPIX Group] Y. Arai *, Y. Ikegami, H. Ushiroda, Y. Unno, O. Tajima, T. Tsuboyama, S. Terada, M. Hazumi, H. Ikeda A, K. Hara B, H. Ishino C, T. Kawasaki D, H. Miyake E, G. Varner F, E. Martin F, H. Tajima G, M. Ohno H, K. Fukuda H, H. Hayashi H, H. Komatsubara H, J. Ida H KEK 、 JAXA A, U. Tsukuba B, TIT C, Niigata U. D, Osaka U. E, U. Hawaii F, SLAC G, OKI Elec. Ind. Co. H (*)—contact person Y. Arai *, Y. Ikegami, H. Ushiroda, Y. Unno, O. Tajima, T. Tsuboyama, S. Terada, M. Hazumi, H. Ikeda A, K. Hara B, H. Ishino C, T. Kawasaki D, H. Miyake E, G. Varner F, E. Martin F, H. Tajima G, M. Ohno H, K. Fukuda H, H. Hayashi H, H. Komatsubara H, J. Ida H KEK 、 JAXA A, U. Tsukuba B, TIT C, Niigata U. D, Osaka U. E, U. Hawaii F, SLAC G, OKI Elec. Ind. Co. H (*)—contact person

3 2006/10/31M. Hazumi (KEK)3 Outline TCAD OverviewTCAD Overview Breakdown voltageBreakdown voltage Effect of bias voltage on readout electronicsEffect of bias voltage on readout electronics P-substrate optionP-substrate option SummarySummary

4 2006/10/31M. Hazumi (KEK)4 TCAD Overview

5 2006/10/31M. Hazumi (KEK)5 What ’ s TCAD ? TCAD ＝ Technology Computer Aided DesignTCAD ＝ Technology Computer Aided Design –Process simulation –Device simulation Finer design rule  more complicated processes, longer development timeFiner design rule  more complicated processes, longer development time TCAD can reduce development time drastically and is necessary for semiconductor manufacturing todayTCAD can reduce development time drastically and is necessary for semiconductor manufacturing today Why not for detector R&D !Why not for detector R&D ! LSI Manufacturing LSI Manufacturing RealVirtual Specifications Function design Logic design Circuit design Layout design Mask fabrication Device production Prototyping Process data Characterization Device data TCAD Process simulation Process simulation Device simulation Device simulation ~3mon. 

6 2006/10/31M. Hazumi (KEK)6 TCAD tools used in this talk Silvaco TCADSilvaco TCAD AHTENA （ Process simulation ） : 2D simulationAHTENA （ Process simulation ） : 2D simulation ATLAS （ Device simulation): 2D or 3D simulationATLAS （ Device simulation): 2D or 3D simulation ENEXSS (Environment for NExt Simulation System)ENEXSS (Environment for NExt Simulation System) Developed by Selete (Semiconductor Leading Edge Technologies, http://www.selete.co.jp/ ）Developed by Selete (Semiconductor Leading Edge Technologies, http://www.selete.co.jp/ ） Full 3D process/device simulation !Full 3D process/device simulation ! ENEXSS example) 3D device simulation for SOI gate drain BOX SOI NMOS  particle injection source source current

7 2006/10/31M. Hazumi (KEK) 7 Diode TEG simulation (unit:  m)

8 2006/10/31M. Hazumi (KEK) 8 Diode TEG simulation baskside fixed at 0V Center (N+) Bulk (N-) Guard (P+) N-substrate P+ > 0  current (unit:  m)

9 2006/10/31M. Hazumi (KEK) 9 Diode TEG simulation Measurements

10 2006/10/31M. Hazumi (KEK)10 TCAD for SOIPIX R&D Handle wafer (i.e. sensor) simulationHandle wafer (i.e. sensor) simulation –Pixel and guard ring design optimization Breakdown voltageBreakdown voltage Charge collectionCharge collection –Problem finding/solving before fabrication Effect of bias voltage on readout electronicsEffect of bias voltage on readout electronics –I/O pads –p-stops for P-substrate option Handle wafer (i.e. sensor) simulationHandle wafer (i.e. sensor) simulation –Pixel and guard ring design optimization Breakdown voltageBreakdown voltage Charge collectionCharge collection –Problem finding/solving before fabrication Effect of bias voltage on readout electronicsEffect of bias voltage on readout electronics –I/O pads –p-stops for P-substrate option Useful to obtain  field maps  device characteristics  signals induced by particles

11 2006/10/31M. Hazumi (KEK)11 Breakdown voltage Results of measurements are reported by H. Miyake: Breakdown voltage ~ 100V at bias-ring edges.

12 2006/10/31M. Hazumi (KEK)12 Breakdown voltage simulation ENEXSS 3D process/device simulation simulated depth = 130  m ~-92V

13 2006/10/31M. Hazumi (KEK)13 Electric field simulation at V bias = -92V

14 2006/10/31M. Hazumi (KEK)14 Breakdown voltage simulation with different configurations  Improvements for the next submission ** Simulation with smaller pixels: lower breakdown voltages than the previous case 90  120  135  150   45V  65V  70V  100V

15 2006/10/31M. Hazumi (KEK)15 Effect of bias voltage on readout electronics

16 2006/10/31M. Hazumi (KEK)16 Back gate effect Backbias should be less than ~8V; otherwise always ON.Backbias should be less than ~8V; otherwise always ON. Problem specific to Monolithic detectorsProblem specific to Monolithic detectors –readout electronics very close to sensors Can we reproduce it with TCAD ?Can we reproduce it with TCAD ? ON Threshold variation (measurements) Back Gate Substrate voltage acts as Back Gate, and changes transistor threshold.

17 2006/10/31M. Hazumi (KEK) 17 Problem Finding with Device Simulation Measurements reproduced With backbias > 8V, NMOS becomes always ON. Substrate voltage under Tr should be kept low. backbias supplied here NMOS handle wafer BOX V B (V) Threshold voltage (V) Backbias (V) -20 -10 0 +10 +20 ENEXSS TCAD

18 2006/10/31M. Hazumi (KEK)18 P+ implantation to reduce back gate effect Weakest part: I/O buffer

19 2006/10/31M. Hazumi (KEK)19 P+ implantation to reduce back gate effect Additional p+ implantation (with voltage fixed at 0V or with some “ anti-bias ” ) should help reduce the back gate effect. How close should they be to the I/O pads ?

20 2006/10/31M. Hazumi (KEK)20 Simulation setup Bulk: N- (~700ohm cm, 6 x 10 12 cm -3 ) BOX NMOS (5  m wide P+, 1 x 10 20 cm -3 ) distance (80, 5, 2  m) Gate threshold voltage at Id= w/L*1e-7 A measured with Vd=1V Backbias (0-20 V) 350  m Should we perform 3D simulation ? Comparison made; results don ’ t show big difference. 2D ~ 10 min., 3D~3days !  choose 2D for this study

21 2006/10/31M. Hazumi (KEK)21 Threshold voltage vs. Bias voltage Large improvement in case of distance = 2  m Vth > 0.25V at VB = 100V ! V_B = 0~20 V 80  m 5  m 2  m distance

22 2006/10/31M. Hazumi (KEK)22 P-substrate option

23 2006/10/31M. Hazumi (KEK) 23 p substrate (1.5k ohm) n+ pixel p+ stop n+ guard ring

24 2006/10/31M. Hazumi (KEK)24 Backgate problem on pixel readout electronics Device simulation  p-stop voltage  0 SOIPIX readout electronics very close to p-stops may suffer from this “backbias”. p-stops ATHENA/ATLAS TCAD

25 2006/10/31M. Hazumi (KEK) 25 Interface charge (qf) qf = 1e13/cm 2 V(p-stop) = -23.5V n+ pixels qf = 0 V(p-stop) = -45V qf = 3e11/cm 2 V(p-stop) = -27.5V Effect depends on irradiation.

26 2006/10/31M. Hazumi (KEK) 26 P-stop optimization V(p-stop) [V] V(p-p) [V]Max. Efield (10 5 V/cm) -23.5-2210 -20-18.510 -14.5-135 -11 9 (1 small pixel in 1 cell) p-stops 2 2 2 1 4 1 1 2 1 2 Best result Cf. 1/1/1 must be even better (common) Vbias = -500V for 250  m thick p-bulk smaller |Vbias| sufficient for thinner detector

27 2006/10/31M. Hazumi (KEK) 27 Pixel configuration  Which is better to avoid microdischarge ?  Which makes the p-stop potential closer to 0 ? 1 small pixel in 1 cell 4 small pixels in 1 cell 20  m (octagon for actual design) 1 large pixel in 1 cell  no difference is seen for qf=1e13/cm 2

28 2006/10/31M. Hazumi (KEK) 28 Choice of pixel design 4 n+ octagons in one pixel individual p-stops p-stop as thin as possible (1  m) p-stop distance as close as possible (1-2  m) 4 n+ octagons in one pixel individual p-stops p-stop as thin as possible (1  m) p-stop distance as close as possible (1-2  m)

29 2006/10/31M. Hazumi (KEK)29 Summary Handle wafer (i.e. sensor) simulationHandle wafer (i.e. sensor) simulation –Pixel and guard ring design optimization Breakdown voltage well understood and new designs proposedBreakdown voltage well understood and new designs proposed –Problem finding/solving before fabrication Effect of bias voltage on readout electronicsEffect of bias voltage on readout electronics –New P+ bias rings proposed for I/O pads –P-substrate option seems more complicated because of p-stops TCAD is very useful for SOIPIX R&D !TCAD is very useful for SOIPIX R&D !

30 2006/10/31M. Hazumi (KEK)30 Backup Slides

31 2006/10/31M. Hazumi (KEK) 31 TCAD at work for sensor R&D (1)

32 2006/10/31M. Hazumi (KEK) 32 TCAD at work for sensor R&D (2)

33 2006/10/31M. Hazumi (KEK) 33 Aluminum (0V) 1000nm distance to the 1 st metal

34 2006/10/31M. Hazumi (KEK)34 End

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