1. DOUBLE-GATE DEVICES AND ANALYSIS 2004. 6. 22 발표자 : 이주용 2004-21599

2. OUTLINE DG-HEMT / VMT  Introduction  Material growth and device fabrication  DC and microwave characteristics  Conclusion

3. DOUBLE GATE HEMT IMPROVEMENT OF HEMT’s PERFORMANCE:  REDUCTION OF GATE LENGTH: (state of the art: Ft=562GHz, Fmax=330GHz for Lg=25nm)  BUT : SHORT CHANNEL EFFECT LIMITATION VERTICAL SCALING LIMITATION PARTICULARLY FOR Fmax

4. INTRODUCTION IMPROVEMENT OF HEMT’s PERFORMANCE:  REDUCTION OF GATE LENGTH: (state of the art: Ft=562GHz, Fmax=330GHz for Lg=25nm) ALTERNATIVE :  BUT : SHORT CHANNEL EFFECT LIMITATION VERTICAL SCALING LIMITATION PARTICULARLY FOR Fmax DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE gate 2 BCB host substrate source drain gate 1 ACTIVE LAYER

5. No buffer layer (reduction of output conductance: Gd) DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE gate 2 BCB host substrate (GaAs) sourcedrain gate 1 ACTIVE LAYER

6. No buffer layer (reduction of output conductance: Gd) Two gate (improvement of transconductance: Gm) (reduction of gate resistance: Rg) (higher intrinsic capacitances: Cgs, Cgd) DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE gate 2 BCB host substrate (GaAs) sourcedrain gate 1 ACTIVE LAYER

7. No buffer layer (reduction of output conductance: Gd) Two gate (improvement of transconductance: Gm) (reduction of gate resistance: Rg) (higher intrinsic capacitances: Cgs, Cgd) DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE Higher 2DEG density in the channel (Reduction of the source and drain resistances: Rs, Rd) gate 2 BCB host substrate (GaAs) sourcedrain gate 1 ACTIVE LAYER

8. No buffer layer (reduction of output conductance: Gd) Two gate (improvement of transconductance: Gm) (reduction of gate resistance: Rg) (higher intrinsic capacitances: Cgs, Cgd) IMPROVEMENT OF THE MAXIMUM OSCILLATION FREQUENCY (Fmax) higher unloaded voltage gain (Gm/Gd) Lower parasitic resistances DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE Higher 2DEG density in the channel (Reduction of the source and drain resistances: Rs, Rd) gate 2 BCB host substrate (GaAs) sourcedrain gate 1 ACTIVE LAYER

9. MATERIAL GROWTH

10.    Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )  Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 ) InGaAs2000 Å InAlAs100 Å InGaAs100 ÅNd 18 cm -3 InAlAs120 Å InAlAs50 Å InGaAs InAlAs50 Å InAlAs120 Å InGaAs Nd 18 cm -3 schottky spacer etch-stop layers InP substrate InGaAs InAlAs InGaAs Nd 18 cm -3 InAlAs 12 InGaAs100 ÅNd 18 cm -3 channel cap layer Cap layer spacer etch- =5.10 100 Å InGaAs

11. MATERIAL GROWTH    Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )  Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 ) InGaAs2000 Å InAlAs100 Å InGaAs100 ÅNd 18 cm -3 InAlAs120 Å InAlAs50 Å InGaAs InAlAs50 Å InAlAs120 Å InGaAs Nd 18 cm -3 schottky spacer etch-stop layers InP substrate InGaAs InAlAs InGaAs Nd 18 cm -3 InAlAs 12 InGaAs100 ÅNd 18 cm -3 channel cap layer Cap layer spacer etch- =5.10 100 Å InGaAs

12. MATERIAL GROWTH ACTIVE LAYER    Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )  Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 ) InGaAs100 ÅNd 18 cm -3 InAlAs120 Å InAlAs50 Å InGaAs InAlAs50 Å InAlAs120 Å InGaAs Nd 18 cm -3 schottky spacer etch-stop layers InGaAs Nd 18 cm -3 InAlAs 12 InGaAs100 ÅNd 18 cm -3 InGaAs2000 Å InAlAs100 Å InP substrate InGaAs InAlAs channel cap layer Cap layer spacer etch- =5.10 100 Å InGaAs

13. MATERIAL GROWTH     InGaAs2000 Å InAlAs100 Å InGaAs100 ÅNd 18 cm -3 InAlAs120 Å InAlAs50 Å InGaAs InAlAs50 Å InAlAs120 Å InGaAs Nd 18 cm -3 schottky spacer InP substrate InGaAs InAlAs InGaAs Nd 18 cm -3 InAlAs 12 InGaAs100 ÅNd 18 cm -3 spacer ACTIVE LAYER =5.10 100 Å InGaAs Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 ) etch-stop layers channel cap layer Cap layer etch- InGaAs2000 Å InAlAs100 Å InP substrate InGaAs InAlAs

14. MATERIAL GROWTH 2 nd HEMT 1 st HEMT     InGaAs2000 Å InAlAs100 Å InGaAs100 ÅNd 18 cm -3 InAlAs120 Å InAlAs50 Å InGaAs InAlAs50 Å InAlAs120 Å InGaAs Nd 18 cm -3 schottky spacer InP substrate InGaAs InAlAs InGaAs Nd 18 cm -3 InAlAs 12 InGaAs100 ÅNd 18 cm -3 spacer ACTIVE LAYER =5.10 100 Å InGaAs Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 ) etch-stop layers channel cap layer Cap layer etch- InGaAs2000 Å InAlAs100 Å InP substrate InGaAs InAlAs

15. MATERIAL GROWTH 2 nd HEMT 1 st HEMT     InGaAs2000 Å InAlAs100 Å InGaAs100 ÅNd 18 cm -3 InAlAs120 Å InAlAs50 Å InGaAs InAlAs50 Å InAlAs120 Å InGaAs Nd 18 cm -3 schottky spacer InP substrate InGaAs InAlAs InGaAs Nd 18 cm -3 InAlAs 12 InGaAs100 ÅNd 18 cm -3 spacer ACTIVE LAYER =5.10 100 Å R ( active layer) = 130 Ω InGaAs Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 )Si-  -doped(5.10 12 cm -2 ) etch-stop layers channel cap layer Cap layer etch- InGaAs2000 Å InAlAs100 Å InP substrate InGaAs InAlAs

16. DEVICE FABRICATION PROCESS

17. CLASSIC HEMT PROCESS (1/4) InP Substrate Active Layer Bonding Pad gate 1 Ohmic Contact InAlAs etch-stop layer InGaAs etch-stop layer  Mesa isolation.  Ni/Ge/Au/Ni/Au Ohmic contact.  Bonding pads. (Ti/Au/Ti)  First T-gate process:  selective recess (Succinic Acid)

18. BONDING PROCESS (2/4)  BCB depositing on both active substrate and on GaAs host substrate.  Bonding. InP Substrate InGaAs etch-stop layer gate 1 Active Layer InAlAs etch-stop layer BCB GaAs host Substrate

19. ETCHING PROCESS (3/4) gate 1 Active Layer BCB GaAs host Substrate  Etching InP Substrate by hydrochloric solution.  Etching InGaAs etch-stop layer by Succinic Acid solution.  Etching InAlAs etch-stop layer by H 3 PO 4 /H 2 O 2 /H 2 O solution.

20. SECOND GATE PROCESS (4/4) gate 1 Active Layer BCB GaAs host Substrate gate 2 Bonding Pad Ohmic Contact  Second T-gate process:  selective recess (Succinic Acid)

21. gate 1 Active Layer BCB GaAs host Substrate gate 2 Bonding Pad Ohmic Contact SEM photograph of a double-gate HEMT gate 2 gate 1 Ohmic contact Active layer

22. DC AND MICROWAVE CHARACTERISTICS

23. W =2x50µm Lg1 = 0.1µm Lg2 = 0.28µm Vg max = 0.2V Vg step = -0.05V V GATE 1 =V GATE 2 Gm ext = 2650 mS/mm Id max = 500 mA/mm V P = -0.2 V  No Kink Effect  Good Pinch-Off I(V) CHARACTERISTICS

24. W =2x50µm Lg1 = 0.1µm Lg2 = 0.28µm Vds = 0.7 V Vgs = 0.1 V MICROWAVE CHARACTERISTICS

25. INTRINSIC PARAMETERS Gm = 3140 mS/mm Gd = 36 mS/mm Gm = 87 Gd DG-HEMT HEMT Gm = 1650 mS/mm Gd = 194 mS/mm Gm = 8 Gd Gm INT Gd INT

26. VELOCITY MODULATION TRANSISTOR

27. INTRODUCTION VMT??  Two channels with differing velocities  Drain current =>controlled by modulating carrier velocity in source-drain channel Fast top channel Slow bottom channel Two channel gate Two gates work in tandem => can maintain total channel population s D Vgt Vgb

28. CHARACTERISTICS Two channel of differing velocity Opportunity for higher speed than C-HEMT HEMT-like Noise Useful in ADCs and AMP Rapid switching time BUT : limited by source-drain transit time top and back gate capacitance should be equal

29. s D Vgt ”HIGH” Vgb ”LOW” t=0 Id=HIGH s D Vgt ”LOW” Vgb ”HIGH” 0<t<tswitch Id=HIGH s D Vgt ”LOW” Vgb ”HIGH” t=0 Id=LOW

30. VMT CONDUCTION BAND ----- + + + AlGaAsGaAsAlGaAs ----- + + + AlGaAsGaAsAlGaAs ( Biased to on ) ( Biased to off )

31. Material growth and device fabrication Top side processing only 600 ℃ 550 ℃ 2um 800 Å 140 Å 300 Å i-AlGaAs (graded)40 Å i-GaAs 200 Å 600 Å Semi insulating GaAs substrate p-GaAs i-AlGaAs n-GaAs i-GaAs i-AlGaAs n-AlGaAs n-GaAs50 Å 450 Å P+ back gate 2 DEG Low mobility channel (Donor ion and As defect) Separate high and low channel Channel isolation and preventing defect

32. EXPERIMENT (1) Sheet carrier concentration Top Lg=40nm Top and bottom channel concentration HEMT channel concentration VMT top channel concentration

33. EXPERIMENT (2) I-V characteristic on state Vgt=-0.85V Vgb=-1.06V off state Vgt=-2.20V Vgb=0V

34. EXPERIMENT (3) Ft=15GHz Fmax=100~600GHz C bottom =K c C top

35. CONCLUSION  0.1µm/0.28µm InAlAs/InGaAs DG-HEMTs:  high extrinsic transconductance = 2650mS/mm  f T = 110GHz f MAX = 200GHz  high unloaded voltage gain (gm/gd = 87)  Velocity Modulation Transistor:  easy fabrication process  low f T but f MAX = 100~600GHz  faster switching time

36. REFERENCE [1] Y. YAMASHITA et al. "Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As HEMTs with an ultrahigh ft of 562GHz" IEEE Electron Device Letters, vol.23, n°10, October 2002, pp.573-575. [2] A. ENDOH et al. "Fabrication technology and device performance of sub-50nm gate InP based HEMTs", Proceeding of IPRM2001, pp.448-451. [3] G.K. CELLER et al. "Frontiers of silicon-on-insulator", Journal of Applied Physics, vol.93, n°9, pp.4955-4978, 2003. [4] M.J.W. RODWELL et al, "Submicron Scaling of HBTs", IEEE trans. on elect.devices,vol.48,n°11,pp.2606-2624,2001. [5] S. B0LLAERT et al, "0.12 μm gate length In0.52Al0.48As/In0.53Ga0.47As HEMTs on transferred substrate", Electron Device Letters, vol.23, n°2, pp.73-75, 2002. [6]Fabrication and operation of a velocity modulation transistor Webb, K.J.; Cohen, E.B.; Melloch, M.R.; Electron Devices, IEEE Transactions on, Volume: 48, Issue: 12, Dec. 2001 [7]Analysis of microwave characteristics of a double-channel FET employing the velocity-modulation transistor concept Maezawa, K.; Mizutani, T.;Electron Devices, IEEE Transactions on, Volume: 39, Issue: 11, Nov 1992 [8]H.Sakaki," velocity-modulation transistor(VMT)-A new field effect transistor concept." Japan.J Appl.Phys vol.21 [9]K.Maezawa, T.Mizutani, and S.Yamada " GaAs/AlAs double-channel structure for velocity modulation transistor."to el published in Japan 1992