1. Ruth Doyle - Intel Ireland Introduction to Transistors Objectives of Lecture 1.Review of Depletion Regions and IV curves 2.Description of PN, NPN and PNP Junctions and the different types of transistors produced 3.Explain how Bipolar Transistors work 4.Describe the characteristics of a MOS Transistor 5.Explain how to bias a MOS transistor 6.Be able to derive the Drain-Source current calculations and understand the voltage conditions required for both saturated and unsaturated conditions of operation 7.Be able to explain how an inverter works 8.Explain what CMOS is and why it is preferred over NMOS only circuits 9.Know how an SRAM Cell works 10.Be able to explain how Parasitic Capacitances are formed and why they cause problems 11.Describe what CMOS Latchup is and how it forms

2. Intel Ireland Depletion Regions and IV Curves Semiconductors are materials which are insulators at zero kelvin but have a small amount of intrinsic conduction at room temperature. They are group IV materials on the periodic table. The can be doped with elements from group III and group V to increase their conductivity. When silicon which has been doped n-type is contacted to silicon which has been doped p-type a pn junction is formed. A depletion region is formed at the junction where excess n and p type carriers neutralise each other. Applying a voltage such that the device is forward bias will cause the depletion region to shrink which applying it in reverse bias will initially expand the depletion region until breakdown ois reached at a high voltage.

3. Intel Ireland PN Junction = Diode 00.51.01.52.02.53.0 JUNCTION BREAKDOWN I D V D VBD IDEAL REAL I D = I S (e q V /KT A - 1) … and what that looks like mathematically… Forward Bias Reverse Bias Delay in current increase until overcome barrier of depletion region. What current would look like in reverse bias if junction didn’t break down Junction Breakdown, what happens in real life

4. Intel Ireland NPN/PNP Junctions There are several ways in which two PN junctions can be connected to each other. Two typical methods produce the MOS transistor and the bipolar transistor. The two transistors are used extensively in IC design because of their different characteristics. P N+N+ N+N+ Gate Source Drain P NN Emitter Base Collector MOS TransistorBi-Polar Transistor

5. Intel Ireland Bi-Polar Transistors The three components are the Emitter (E), Base (B) and Collector(C). The gate is connected to the Semiconductor (produces heat) Quiescent State: Emitter/Gate at same bias. No current. E/B current is limited by intrinsic field, B/C junction is reverse- biased. Conducting State: VE < VB << VC (NPN type) –Emitter/Base = Forward Biased. Base/Collector = Reverse Biased. –This Bias is the same as for MOS device. –Emitter/Base field extends almost to Collector. Forward bias injects minority carriers into narrow Base. These carriers immediately drift to B/C junction, and the B/C electric field accelerates them into Collector.

6. Intel Ireland Bi-Polar Transistors The NPN junction shown below is a basically two diodes. The np junction on the emitter side (emitter base) is in forward bias while the pn junction on the collector side (base collector) is in reverse bias. In a reverse biased pn junction the constant reverse saturation current is largely independent of the bias voltage. However the rate of injection of charge carriers can be controlled by the forward biased np junction. N+N+ PN EmitterBaseCollector 00.51.01.52.02.53.0 JUNCTION BREAKDOWN I D V D VBD IDEAL REAL I D = I S (e q V /KT A - 1) Constant reverse saturation current independent of bias voltage

7. Intel Ireland To explain the workings of the bi-polar transistor its more useful to look at it in terms of energy levels. N P N In each of the N-type layers conduction can take place by the free movement of electrons in the conduction band. In the P-type layer conduction can take place by the movement of the free holes in the valence band. In the absence of any externally applied electric field, depletion zones form at both PN-Junctions, so no charge moves from one N layer to the other. Emitter BaseCollector

8. Intel Ireland When a reverse bias voltage is applied between the base and collector the energy bands change as such, N P N The polarity of the applied voltage widens the depletion region between the collector and base and so no current will flow. Large V

9. Intel Ireland N P N Small V If a voltage is now applied to the emitter and base which forward biases this junction, the following happens to the energy bands and current flow. Electrons are pushed from the emitter into the base region. Once there the electrons can respond to the attractive force from the positively-biased collector region. The result is an emitter-collector current whose magnitude is set by the chosen emitter-base voltage we have applied. Large V

10. Intel Ireland N P N Large V Small V IBIB IEIE Some of the electrons from the emitter will end up recombining with a hole in the base. The result is that the base loose some of its positive charge. This needs to be replenished to ensure the base does not become more negative (and prevent electron flow). The emitter-base voltage removes captured electrons to maintain hole numbers. A current flows then in this part of the circuit that is about 100 times smaller than the base collector current

11. Intel Ireland So in the configuration shown here the emitter side of the device injects electrons into the base which are then collected to yield the collector current. For a good bi-polar transistor almost all of the electrons injected into the base should be collected by the collector. For this to happen the base needs to be very narrow (the neutral length of the base needs to be much smaller than the electron diffusion length). The current through the emitter base should be compose almost entirely of electrons injected from the emitter rather than holes from the base to the emitter. This can be achieved by heavily doping the emitter and only lightly doping the base. PN EmitterBaseCollector N+N+ e-e-

12. Intel Ireland MOS Transistor The three components are the Source (S), Gate (G) and Drain(D) Gate is TOTALLY insulated from Semiconductor Current will be Minority Carriers of substrate under Gate! Quiescent State: Gate is reverse voltage of substrate (- for p- type and + for n-type.) This repels/depletes silicon below gate (between S and D) of any minority carriers. Conducting State: Gate is same as substrate (+ for p-type and – for n-type substrate). oGate pulls minority carriers from substrate to thin layer (5nm) connecting Source and Drain with their majority carriers. oForward bias of Source/Gate injects majority carriers into thin layer. oBias of Gate/Drain creates field that pulls majority carriers into Drain.

13. Intel Ireland Biasing of a MOS Transistor P N+N+ N+N+ 3 volts V ds 0.7 volts V gs With the switch open there is no potential applied to the gate. There is no conduction path between the source and drain and so no current flows + ++++ - - - - - - - When the switch is closed, a positive voltage is applied to the gate. This positive charge attracts out the intrinsic negative charge carriers in the bulk silicon. This forms a channel of continuous charge allowing current to flow between the source and drain

14. Intel Ireland The MOS transistor is therefore just a switch. No current ever flows from the gate to the substrate under any bias. The gate has to be totally insulated from the source, drain and substrate. A small voltage applied to the gate determines whether current flows between the source and drain. A very small change in the gate source voltage can yield a substantial change in the drain source current that flows. While there is an initial linear increase in drain/source current with drain/source voltage, this does level off into saturation mode.

15. Intel Ireland 600 500 400 300 200 100 0 V GS = +5V V GS = +4V V GS = +3V V GS = +2V V GS = +1V 0 1 2 3 4 5 6 Drain-Source Voltage, V DS (volts) Drain Current, I DS (  a) Saturation Region Linear Region Example of Characteristics Curves of an N- channel MOSFET

16. Intel Ireland Calculation of I ds The whole idea of a MOS transistor is to use a voltage on the gate to induce a charge into the channel region between the source and drain so that current can flow under the influence of the electric field created by the voltage applied between the two. Since the charge induced depends on the voltage applied to the gate V gs, then the current between the source and drain I ds will depend V gs and the voltage applied between the source an drain, V ds. The transit time is given as:

17. Intel Ireland The velocity is then defined as: where μ is the electron/hole mobility and E ds is the electric field applied across the source and drain The electric field is given as the voltage over the channel length, All this can be used to define the transit time in the source drain region, As stated before charge is induced in the channel due to gate voltage V gs

18. Intel Ireland The voltage drop along the channel though is linear with distance x from the source (due to the IR drop in the channel). Assuming then that the device is unsaturated, the average voltage drop along the channel will be, Since there is a threshold voltage (V t ) required to invert the charge under the gate, this means that the effective gate voltage is, Given that charge per unit area is E g ε ins ε o The induced charge in the channel is then, where Eg is the average E field gate to channel, ε ins is the relative permittivity of the gate insulator, ε o is the permittivity of free space, W is the width of the gate and L is the length of the channel

19. Intel Ireland The average electric field Eg (from the gate to the channel) can be defined in terms of the voltage drop across the insulating oxide and its thickness; So the induced charge can be defined as, and the drain source current therefore defined as,

20. Intel Ireland This equation can also be written as where Saturation begins when V ds = V gs – V t since the IR drop in the channel now equals the effective gate to channel voltage at the drain and the current remains fairly constant as V ds increases further. Therefore, These expressions of current are valid for both depletion and enhancement mode devices. C ox is the capacitance per unit area of the oxide

21. Intel Ireland Enhancement and Depletion Mode Since the MOS transistor is just a switch it can be designed to be continuously on in standby mode or continuously off. These conditions are defined as enhancement and depletion mode transistors. MOS Type ModeStandby Condition Vgs switching Structure n-MOSdepletionOn- n-MOSenhancementOff+ p-MOSdepletionOn+ p-MOSenhancementOff- P N+N+ N+N+ Source Drain Gate N P+P+ P+P+ Source Drain Gate P Source Drain Gate N+N+ N+N+ N Source Drain Gate P+P+ P+P+

22. Intel Ireland Inverters The most basic part of any integrated circuit is the inverter, which gives the ability to change a “on” signal into an “off” signal. In Out 5V 0V Input Output NMOS Enhancement (off in standby) NMOS Depletion (on in standby) Hi Lo Hi Lo 5V The depletion transistor switches off while the enhancement one switches on. This results in a “Lo” output 0V Now the depletion mode transistor switches on while the enhancement mode one switches off, yielding a “Hi” output The circuit could also be produced using two pmos transistors, again one enhancement and one depletion

23. Intel Ireland CMOS – Complimentary Metal Oxide Silicon Originally pmos technology only was used for integrated circuits, this changed in the mid seventies when it became apparent that nmos technology was required for speed. In 1974 the 8080 was produced using nmos technology only. Late into the 1970’s nmos technology started to suffer from power consumption problems and so CMOS has become the technology of choice since the early 80’s. This involves using both nmos and pmos transistors to produce inverters (the basic building block of any IC) The CMOS advantage is that the output of a CMOS inverter can be as high as the power supply voltage and as low as ground. This large voltage swing and the steep transition between logic levels yield large operation margins and therefore also a high circuit yield. In addition, there is no power dissipation in either logic state. Instead the power dissipation occurs only when a transition is made between logic states.

24. Intel Ireland CMOS Inverter The CMOS inverter is produced using a single pmos and a single nmos transistor. The big advantage of this circuit is that neither transistor is in a constant “on” state and so power dissipation is much less than using only NMOS or only PMOS transistors In Out 5V 0V NMOS Transistor PMOS Transistor Input Output Hi Lo Hi Lo A positive input causes the NMOS transistor to switch on. The PMOS one remains off resulting in a “Lo” output A negative or Lo input, switches the NMOS transistor off A PMOS transistor, switches on resulting in a “Hi” output.

25. Intel Ireland SRAM Cell The SRAM cell is a six transistor unit that is used extensively in CPU design. Bit 1 Line Bit 2 Line Word Line +V To read the contents of the cell, the two bit lines are pre-charged high. The word line is then enabled If a 1 is stored in the cell Bit 1 Line will be discharged. If a 0 is stored in the cell the Bit 2 Line will be discharged To write a 1 to the cell, Bit 1 Line is forces to 0 This force a zero to the gate of the 2 nd PMOS This in turns forces the output of this inverter to high latching a 1 into the gate of the first inverter

26. Intel Ireland P Gate Source Drain N+N+ N+N+ Parasitic Capacitances A problem with all pn junction transistors is the inherent parasitic capacitances that are created. These capacitances both slow down the device and can cause latch-up, a condition which gives rise to the establishment of low resistance conductance paths between the source and drain. Everywhere there is a pn junction, a diode is formed. A depletion region (and hence a capacitance) exists. The gate oxide itself also forms a capacitor, not only with the substrate but also the source and drain.

27. Intel Ireland Latch-Up While CMOS cell have many advantages over NMOS or PMOS transistors alone, they do suffer with one major issue …….. Latch-Up !!! This is a condition which designers are very aware of as it can cause a functioning part to fail completely. As shown on the previous slide, diode are formed anywhere there is p-type material in contact with n-type material. In a CMOS device it is possible to unintentionally have PNP and NPN transistors form and provide paths of lower resistance resulting in constantly on transistors which burn-out. Latchup may be induced by glitches in the power supply rail or even by incident radiation

28. Intel Ireland Latch-Up Formation The substrate which is N-well is connected via an N+ diffusion tap to Vcc while the P-well is terminated at ground. There are effectively two transistors and resistors forming a path between V cc and Ground. If sufficient substrate current flows such that the voltage across R1 can turn on T1, this will then draw current through R2 which can generate sufficient voltage to turn on T2. N - Well P- Well N+N+ N+N+ P+P+ P+P+ P+P+ N+N+ Gnd V cc V in V out R1 R2 T2 T1