1. FPGA Technology Overview Carl Lebsack * Some slides are from the “Programmable Logic” lecture slides by Dr. Morris Chang

2. What’s an FPGA? FPGA – Field Programmable Gate Array

3. Standard Logic ASIC Full custom ICs Cell-Based ICs Gate Arrays Programmable Logic Devices FPGAs CPLDs SPLDs FPICs

4. How do you make a “Programmable” circuit? One time programmable Fuses (destroy internal links with current) Anti-fuses (grow internal links) PROM Reprogrammable EPROM EEPROM Flash SRAM - volatile } non-volatile

5. How do you program an FPGA? Create a circuit design Graphic circuit tool Verilog VHDL AHDL Compile the design for the selected device Download the compiled configuration

6. FPGAs offer many advantages over ASICs Small development overhead No NRE (non-recurring engineering) costs Quick time to market No minimum quantity order Reprogrammable

7. What are the Guts of an FPGA? Basic Components LUT (look-up-table) Flip-Flops Multiplexors I/O Blocks Programmable switching matrices Interconnect Clocks

8. Configurable Logic Blocks I/O Blocks Programmable Interconnects Xilinx FPGA Structure

9. CMOS SRAM Cell

10. 3-LUT 0110100101101001 input[0:2] output config_in clock config_out

11. 2 Slice CLB

12. LE

13. LAB

15. IOB

16. More Guts Additional components RAM blocks Dedicated multipliers Tri-state buffers Transceivers Processor cores DSP blocks

17. Dedicated Arithmetic Structures in FPGAs Altera Xilinx QuickLogic

18. Power PC in Virtex-II Pro Embedded 300+ MHz Harvard Architecture Core Low Power Consumption: 0.9 mW/MHz Five-Stage Data Path Pipeline Hardware Multiply/Divide Unit Thirty-Two 32-bit General Purpose Registers 16 KB Two-Way Set-Associative Instruction Cache 16 KB Two-Way Set-Associative Data Cache Memory Management Unit (MMU) - 64-entry unified Translation Look-aside Buffers (TLB) - Variable page sizes (1 KB to 16 MB) Dedicated On-Chip Memory (OCM) Interface Supports IBM CoreConnect™ Bus Architecture Debug and Trace Support Timer Facilities

19. Excalibur Embedded Solution Excalibur Processor Logic High Performance I/O Memory Complete SOPC Solution Integrates Embedded Processors With Programmable Logic Device Delivers System-on-a-Programmable-Chip (SOPC) ─ Programmable Flexibility PLD Hardware Embedded Software ─ Compute Performance High Performance Processor Data Path Hardware ─ Customer Configuration Microprocessor Peripherals Hardware Logic ─ Faster Time-to-Market

20. ARM in Excalibur Industry-standard ARM922T 32-bit RISC processor core operating up to 200MHz ─ ARMv4T instruction set with Thumb extensions ─ Memory management unit (MMU) included for real-time operating systems (RTOS) support ─ Harvard cache architecture with 64-way set associative separate 8- Kbyte instruction and 8-Kbyte data caches Embedded programmable on-chip peripherals ─ ETM9 embedded trace module to assistant software debugging ─ Flexible interrupt controller ─ Universal asynchronous receiver/transmitter (UART) ─ General-purpose timer ─ Watchdog timer

21. Altera DSP-Block-Configuration Options and Features

22. FPGAs come in a wide variety Xilinx Slices/CLBs PowerPC cores Altera LEs/LABs ARM cores/Softcores Numbers of subcomponents varies Special features vary Manufacturers use own terminology

23. FeatureEP1S10EP1S20EP1S25EP1S30EP1S40EP1S60EP1S80EP1S120 Logic Elements (LEs)10,57018,46025,66032,47041,25057,12079,040114,140 M512 RAM Blocks ( 512 Bits + Parity) 941942242953845747671,118 M4K RAM Blocks (4 Kbits + Parity) 6082138171183292364520 M512 RAM Blocks (512 Kbits + Parity) 122446912 Total RAM bits920,4481,669,2481,944,576 3,317,184 3,423,744 5,215,104 7,427,520 10,118,016 DSP Blocks610 1214182228 Embedded Multipliers4880 96112144176224 PLLS6661012 Maximum User I/O Pins4265867067268221,0221,2381,314 Engineering Sample Availability Now Use Production Use Production N/ANowN/ANow2003 Production Device Availability March 2003 Now March 2003 April 2003 January 2003 Stratix Device Overview

24. FPGA Design Main components are generally done as custom designs Layout is very regular and automation could assist in cell placement

25. Stratix FPGA Layout

26. year199519961997200020032004 ? Technology0.6µ0.35 µ0.25 µ0.18 µ0.13 µ0.07µ Gate count25K100K250K1 M 100K LC* 8Mb RAM 400 18X18 multipliers Transistor count 3.5M12M23M75M430M1B PLD device density and VLSI technology *note: Xilinx Virtex-II Pro XC2VP100 (9/16/2003)

27. More Information www.xilinx.com www.altera.com