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BO1-1 Calorimeter Trigger 402.06.03 W. H. Smith, L3 Manager, Calorimeter Trigger, 402.06.03 Director’s Review Rehearsal January 15, 2016 15-Jan-2016 W.

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Presentation on theme: "BO1-1 Calorimeter Trigger 402.06.03 W. H. Smith, L3 Manager, Calorimeter Trigger, 402.06.03 Director’s Review Rehearsal January 15, 2016 15-Jan-2016 W."— Presentation transcript:

1 BO1-1 Calorimeter Trigger 402.06.03 W. H. Smith, L3 Manager, Calorimeter Trigger, 402.06.03 Director’s Review Rehearsal January 15, 2016 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 1

2  WBS definition  Basis of Estimate  Schedule  Cost and Labor Profiles  Risk and Contingency  R&D status and plans  ES&H and QA  Summary 2 Outline Phase 2 Calorimeter Trigger Upgrade15-Jan-2016 W. Smith

3 3 402.0X Organization Chart to L3 (L4 for tracker) Phase 2 Calorimeter Trigger Upgrade15-Jan-2016 W. Smith 402.06 Trigger Jeff Berryhill (FNAL) 402.06.03 Calorimeter Trigger Wesley Smith (UW) 402.06.04 Muon Trigger Darin Acosta (UF) 402.06.05 Track Correlator Rick Cavanaugh (UIC)

4 WBS Definition 4 Phase 2 Calorimeter Trigger Upgrade15-Jan-2016 W. Smith

5  402.06.03.01 Regional Cards M&S  402.06.03.02 Global Cards M&S  402.06.03.03 Fibers and Cables M&S  402.06.03.04 Crates and Infrastructure M&S  402.06.03.05 Electrical Engineering Labor  402.06.03.06 Electrical Technician Labor  402.06.03.07 Firmware Engineering Labor  402.06.03.08 Software Engineering Labor  402.06.03.09 Travel 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 5 402.06.03 WBS

6  EB/EE/HB/HE: Process individual readout granularity cells to be optimally matched with track trigger information  Produce Tau, Jet, e/γ clusters….  HGCAL produces Tau, Jet, e/γ clusters… as part of TPG  Data processed by input Layer 1 and then final Layer 2 providing the output. Similar to current calorimeter trigger, essentially scaled to higher number of channels involved.  Tasks: Isolation, duplicate removal, boundaries, global energy sums  Produces/refines candidate objects/clusters to send to the different track correlator processors o Logic is based on adaptation of Particle Flow ideas to L1T o Different correlators for muons, e/γ, Tau, Jet….  Also provides stand-alone calorimeter trigger 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 6 Calorimeter Trigger Design

7 Crate BCrate CCrate A HCALECALHCALECALHCALECAL Processor Track Correlator …… Regional Processing: Global Processing: Model for L1 Cal. Trigger Hardware 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 7 Base processors on existing CMS Virtex7 trigger processor cards cluster ECAL using fine granularity information for e/γ candidates for track matching/veto + track isolation, and use wider H clusters behind for veto, etc.

8 L1 Calorimeter Trigger Upgrade  Calorimeter Trigger:  Process individual crystal energies instead of present 5x5 towers  Higher resolution matching to tracks: ΔR < 0.006  Improvement in stand- alone electron trigger efficiency + rate→ 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 8

9  M&S costs are based on escalated prices of similar components used for the Phase 1 upgrade of the L1 trigger. Details on next slide  Labor costs are estimated from engineers currenlty on staff, or on standard rates as needed. Effort calculated as per the Phase 1 Trigger Upgrade Project.  International travel is estimated at $3K per trip, and domestic travel is estimated at $1K per trip. 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 9 Basis of Estimate

10 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 10 Cost Estimate (from CMS Phase 2 TP) EB61200# of xtals EE61000 Use # of Shashlik channels temporarily until #’s from HGCAL available HB/HE13824From HCAL Phase 1 HF1728 From HCAL Phase 1 but combine 2 measurements/PMT Information per channel12assume 10 bits energy and 2 bits quality Total Bits1653024 Bandwidth6.61E+13Data transmitted at 40 MHz Card BW4.92E+11 Assume present cards with 80x10 Gbps links running 192 bits at 40 MHz with 80% packing efficiency No. cards in Layer 1135 This number of cards asumes the present MP7 Add 33% more cards for Layer 2179 Multiply by 15 kCHF/card + 15% Spares + 16 kCHF/12 Cards Infrastucture3488 NB: Estimate done with Phase 1 CTP7 (Virtex7) card capabilites and costs. For Phase 2 Expect UltraScale, Ultrascale+ FPGA costs higher, but fewer boards used.

11 Phase 2 Trigger Project Schedule This is intentionally a “conceptual schedule” and is not intended to suggest that a full resource-loaded schedule has been developed 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 11

12  Placeholder 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 12 Cost and Cost Profile

13  Placeholder 13 Risk and Contingency Phase 2 Calorimeter Trigger Upgrade15-Jan-2016 W. Smith

14  Safety: follows procedures in CMS-doc-11587, FESHM  L2 Manager (W.S.) responsible for applying ISM to trigger upgrade. o Under direction of US CMS Project Management.  Modules similar to others built before, of small size and no high voltage  Quality Assurance: follows procedures in CMS-doc-11584  Regularly evaluate achievement relative to performance requirements and appropriately validate or update performance requirements and expectations to ensure quality.  QA: Equipment inspections and verifications; Software code inspections, verifications, and validations; Design reviews; Baseline change reviews; Work planning; and Self-assessments.  All modules have hardware identifiers which are tracked in a database logging QA data through all phases of construction, installation, operation and repair.  Graded Approach:  Apply appropriate level of analysis, controls, and documentation commensurate with the potential to have an environmental, safety, health, radiological, or quality impact.  Four ESH&Q Risk levels are defined and documented in CMS-doc-11584. 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 14 Trigger ESH&Q

15  After full testing at institute, shipped to CERN  All tests recorded (of all types) for individual boards in database  Tests use and validate software and firmware test release  Acceptance Testing in Electronics Integration Center (EIC) at CERN  Individual labs for CSC and Calorimeter Trigger  Boards retested to validate institute test results  Tests use software and firmware test release  Integration Testing in EIC  Row of racks with DAQ, Trigger, Central Clock, Crates of other subsystem electronics  Operation of a vertical slice with electronics to be tested installed.  Tests use and validate software and firmware commissioning release  Integration Testing at P5: Global Runs/Parallel Operation  Test with all CMS with cosmics when beam not running/with beam when running  Electronics installed in final locations with final cables  Full-scale tests with full CMS DAQ/Trigger/Clocking  Tests use software and firmware commissioning release  Post commissioning Operations at P5: Global Runs/Parallel Operation  After testing completes, continue with Global Runs/Parallel Operation  Validate software and firmware initial operational release 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 15 QA/QC: Testing and Validation

16 Phase 2 Trigger Algorithm R&D  Goal:  Allow development of calorimeter, correlation trigger electronics – specify: o Planned Algorithms o Necessary trigger primitives o Link counts and formats  Plan:  Initial definition of trigger algorithms, primitive objects and inter- layer objects (TP.L1.1) – 2Q2016  Baseline definition of trigger algorithms, primitive objects and interchange requirements with subdetectors. (TP.L1.3) – 2Q2017  Detailed Software emulator demonstrates implementation of core phase 2 trigger menu with baseline objects (TP.L1.4) – 4Q2017 o Used to inform the final implementation of the trigger hardware. 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 16

17 Phase 2 Trigger Hardware R&D - I  2 R&D activities:  Calorimeter Trigger Processor  Track Correlator Processor  Hardware R&D Milestones - I  Initial demonstration of key implementation technologies (TP.L1.2) – 4Q2016 o e.g. > 25 Gb data links, general applicability across Phase 2 o Start Construction of initial prototype circuits for demonstration of feasibility of trigger design, leads to:  Definition of hardware technology implementation baseline (TP.L1.5) – 1Q2018 o Testing and revisions of prototypes. o Used with algorithm and emulation baseline to define what is needed for → 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 17

18 Phase 2 Trigger Hardware R&D - II  Hardware R&D Milestones – II  Full-function prototypes produced which allow local comparison with emulator (TP.L1.6) – 4Q2018 o First boards which have sufficient channels, processing capability and bandwidth optical links to meet the requirements of the final boards o These boards will cover only a portion of the trigger processing logic, however, and only local comparisons will be possible between hardware behavior and the emulator.  Demonstrator system shows integration and scaling, global/full- chain comparison with emulator (TP.L1.7) – 4Q2019 o End-to-end comparisons over a slice of the detector which include multiple full-capability prototype boards and the prototype full-capability infrastructure o Goal of demonstrating a prototype system with its infrastructure and testing environment capable of being connected to its front end detector for test-beam validation to follow.  Final Milestone:  Phase 2 Trigger TDR (TP.L1.8) – 1Q2020 o Based on results from Trigger Demonstrators. 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 18

19  Phase 1 upgrade: two generations (V5, V6) before production boards—similar path reasonable for Phase 2  Phase 2 upgrade working terminology:  “APDx”—Advanced Processor Demonstrator, APD1 for gen-1, APD2 for gen-2, etc. o Evolution of the successful CTP7 architecture, staying current with advances in FPGA, SoC, PCB, embedded OS and optical technologies o Supported by simpler auxiliary boards as necessary (RTMs, etc.)  APM—Advanced Processor Module—Phase 2 production platform  Today: CTP7 a very capable “Gen 0” demonstrator  Supporting Phase 2 Tracking Trigger and Calorimeter Trigger R&D  Comparatively “young” platform (< 2 years old) w/ new technology  Receiving interest from other groups as an upgrade and/or Phase 2 R&D platform 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 19 Phase 2 Cal. Trig. Demonstrators

20  CTP7 “Gen zero” demonstrator  12 MGT MicroTCA backplane links  67 Rx and 48 Tx 10G optical links  Modular V7 firmware architecture for ease of customization  Currently have 4 different configurations in P5 and R&D use 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 20 CTP7 as a Phase-2 Demonstrator 12 Backplane MGT Connections (plus DAQ) 10G capable frontpanel optical links, 67 Rx and 48 Tx

21  MicroTCA.0—the MicroTCA for Phase 1  MicroTCA.4—a standard with a rear transition module (RTM) about the same size as a double-width AMC  MicroTCA.4 shares payload power between AMC and RTM  New Vadatech chassis (VT815) supports 12 full size AMC+RTM combinations with 120W per slot  ATCA—older standard, physically larger  Shape of the RTM in ATCA limits its utility, but overall ATCA provides about 2X the board and frontpanel area as MicroTCA.4  IPMI: CMS-common IPMI solutions (MMC, System Manager) supplied by Wisconsin can easily migrate to ATCA  Board costs and FPGAs  Xilinx UltraScale at about same cost/gate as Virtex-7, but gate/MGT ratios are higher in UltraScale—MGTs drive part selection in CMS  FPGA costs are going to dominate over form factor costs in the high performance applications 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 21 Upgrade Form Factors

22 Processi ng FPGA(s)  Next-gen FPGA and ZYNQ SoC devices  General upgrade to embedded Linux platform over CTP7  Direct optical interfaces for the ZYNQ PL section  DDR4 SDRAM on main FPGA for higher density and bandwidth  Optical module mix for compatibility with current and next-gen optical links 15-Jan-2016 W. Smith Phase 2 Calorimeter Trigger Upgrade 22 APD Architecture Example Processin g FPGA(s) ZYNQ SoC High BW DDR4 SDRAM System Memory GbE Control Path Optical Interfaces Front Side Optical Interface Flash File System Flash File System Backplane/RTM MGT Links

23 Summary 23 Phase 2 Calorimeter Trigger Upgrade15-Jan-2016 W. Smith

24  R&D Program will result in designs for the Trigger Upgrade that will meet technical performance requirements  Scope and Specifications of Trigger Upgrade are sufficiently well-defined to support the C&S estimates  Upgrade based upon common hardware platforms and components  ES&H, QA plans, C&S based on experience with original trigger construction and Phase-1 upgrade  Management and Engineering teams are experienced with sufficient design skills, having designed and built original CMS trigger and Phase-1 Upgrade 26 August 2013, Wesley Smith CD-1 Review -- P05: Trigger Upgrade 24 Conclusions


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