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18 th September 2014 1 EREMS 16 th - 18 th September 2014 PRESENTATION SANDRINE ZAOUCHE & REMI SARRERE.

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Presentation on theme: "18 th September 2014 1 EREMS 16 th - 18 th September 2014 PRESENTATION SANDRINE ZAOUCHE & REMI SARRERE."— Presentation transcript:

1 18 th September 2014 1 EREMS 16 th - 18 th September 2014 PRESENTATION SANDRINE ZAOUCHE & REMI SARRERE

2 18 th September 2014 2 1 / INTRODUCTION 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion ● Feedback about flight FPGA based on project examples ● Table of contents - 1 / Introduction - 2 / EREMS presentation - 3 / Choice of FPGA target - 4 / Prototypes - 5 / Design - 6 / Performance - 7 / Programming - 8 / Conclusion PROJECT NAME: FPGA USED – Main feature, main functions PROJECT NAME:FPGA USED– Main feature, main functions

3 18 th September 2014 ● EREMS, French SME near Toulouse (since 1979) space flight electronics - specialized in the design & manufacture of space flight electronics ● Means & facilities - 62 employees (36 engineers) - Clean room facilities - Space Qualified processes - Space Certified operators & controllers ● Development / supply of space electronic equipments - power supplies and power distribution units - control/command electronics - onboard computers, data handling equipment - front end electronics, video acquisition equipment ● References CPUGEN (Leon3 OnBoard Computing Module) - R&T: CPUGEN (Leon3 OnBoard Computing Module) BEPICOLOMBO/PHEBUS, JASON-3/CARMEN, TARANIS - Scientific programs: BEPICOLOMBO/PHEBUS, JASON-3/CARMEN, TARANIS PHASE B STUDY / PVL - Observation satellites: SPOT 6 & SPOT 7, PHASE B STUDY / PVL - Telecom programs: EUROSTAR 3000, IRIDIUM-Next 3 2 / EREMS PRESENTATION 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion

4 18 th September 2014 4 3 / CHOICE OF FPGA TARGET TARANIS: 1 RTAX1000 + 2 RTAX2000 – PHOTOMETRE analyzer, triggering CPUGEN: 1 ATF280  1 ATFS450 –ITAR free Leon3 computing board TARANIS: 1 RTAX1000 + 2 RTAX2000 – PHOTOMETRE analyzer, triggering CPUGEN: 1 ATF280  1 ATFS450 –ITAR free Leon3 computing board ● Requirements identification - analysis of function (sequencing, signal treatment) - implementation of existing/developing IPs: microcontroller: 8051 computing: PID, divider compressor: Elias, FELICS, RLEEDAC: Hamming, Reed-Solomon communication: SpaceWire, 1553, UART - space available on the board ● Resources estimation FPGA size + IO number - FPGA size + IO number ● FPGA selection ● Feedback : 2 helpful criteria PIN compatibility for 1 FPGA family - PIN compatibility for 1 FPGA family RTSX32/72 RTAX250/1000/2000 (TARANIS) ATF280/S450 (CPUGEN) QFP package - QFP package preferred to CCGA 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion

5 18 th September 2014 5 4 / PROTOTYPES ● One Time Programmable FPGA (OTP) : 3 or 4 steps 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion

6 18 th September 2014 6 4 / PROTOTYPES ● One Time Programmable FPGA (OTP): 3 or 4 steps CARMEN: 2 RTSX – Data processing, including microprocessor PHEBUS: 1 RTAX1000 – Data processing, imaging, IPprocessor PVL: 1 RTAX2000 D– Filtering, interpolation CPUGEN: 1 ATF280  1 ATFS450 –ITAR free Leon3 computing board CARMEN: 2 RTSX – Data processing, including microprocessor PHEBUS: 1 RTAX1000 – Data processing, imaging, IPprocessor PVL: 1 RTAX2000 D– Filtering, interpolation CPUGEN: 1 ATF280  1 ATFS450 –ITAR free Leon3 computing board 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion ● Programmable FPGA: 2 steps Some prototypes of programmable flight FPGA are quite expensive Prototype ATF280 vs. Flight ATF280 cost ratio ≈ 1/3 Does the same package follow the whole flow? Does a low-cost FPGA exist with the same matrix technology? - Does the same package follow the whole flow? Most of programmable FPGA and OTP FPGA have different packages adapter layout to have the programmable fit the OTP (CARMEN) double-prints on the same board (PHEBUS) - Does a low-cost FPGA exist with the same matrix technology? No FPGA exists with DSP blocks to prototype RTAX2000D (PVL) Xilinx prototype + adapter layout or socket to fit with the final package Prototype RTAX2000D vs. Flight RTAX2000D cost ratio ≈ 1/10

7 18 th September 2014 7 5 / DESIGN TARANIS: 1 RTAX1000 + 2 RTAX2000 – PHOTOMETRE analyzer, triggering CPUGEN: 1 ATF280  1 ATFS450 –ITAR free board including microprocessor TARANIS: 1 RTAX1000 + 2 RTAX2000 – PHOTOMETRE analyzer, triggering CPUGEN: 1 ATF280  1 ATFS450 –ITAR free board including microprocessor ● LIBERO - 6 updates between 01/2011 and 02/2012 for the version 9.1 + updates of Simplify + CN1410 (TARANIS) - several warnings before the last version 9.2 SP1 relatively new version to be used for current flight FPGA ● PRECISION ( version 2012c.14 OEM_ATMEL ) - LPM_MUX (ATF280) was not properly synthesized by the software (CPUGEN) comparison between functional & post synthesis simulations - short license validity for significant cost ● FIGARO - unintuitive handling despite the good reactivity of the customer support 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion

8 18 th September 2014 8 6 / PERFORMANCE ProjectFPGA Matrix Working Frequency Occupancy rateMain Functions ExpectedReached JASON 2T2L2RTSX72100 MHz105 MHz99% FF; 47% Cb; 100% IOTime Transfer by Laser Link CARMEN (Icare-NG) MicroRTSX7232 MHz42 MHz82% FF; 45% Cb; 96% IOMicro-processor companion Exper.RTSX7232 MHz39 MHz91% FF; 87% Cb; 95% IO Test of components in radiative environment PHEBUS (Bepi-Colombo) RTAX1000 40 MHz 10 MHz 51 MHz 15 MHz 102 MHz 82% FF; 80% Cb; 92% IO; 58% RAM 8051µC (IP MICROSEMI), image processing, image compressions (coordinate, binary, Elias) TARANIS PHARTAX100020 MHz61 MHz 59% FF; 26% Cb; 66% IO; 86% RAM Analog signal acquisition, event trigger (ration algorithm) MCARTAX2000 50 MHz 20 MHz 57 MHz 70 MHz 91% FF; 83% Cb; 95% IO; 77% RAM Image compressions (FELICS, RLE), PID Thermal control XGRERTAX2000 50 MHz 3x 20 MHz 63 MHz 134 MHz 69 % FF; 51% Cb; 97%IO; 82% RAM Spectrum generation, event trigger PVL (study) RTAX2000D100 MHz99 MHz 44% FF; 28% Cb; 0% RAM; 97% DSP Signal demodulation, filtering and interpolation CPUGEN (R&T) ATF280 Compatible ATFS450 20 MHz21 MHz 8% Cells; 7% Nets; 65% IO; 1% RAM Leon3 boot and board management 90% cells free for user applications 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion

9 18 th September 2014 9 7 / PROGRAMMING 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion ● Equipment needed - OTP FPGA 1 programmer + (1 socket / package) - Programmable FPGA 1 probe ● Feedback about Microsemi FPGA - 224 OTP flight FPGA programmed - 3.13% failed mature process

10 18 th September 2014 10 8 / CONCLUSION ● Expectations for future flight FPGA: free from exportation restrictions - free from exportation restrictions pin compatible FPGA - member of a pin compatible FPGA family low cost - low cost flow for prototypes hard IPs: - integration of hard IPs: communication modules (SpaceWire, 1553 bus, CAN bus, Ethernet, SPI) multiplier-accumulator blocs RAM blocs LVDS compatibility microprocessor core user friendly - user friendly development tools for: synthesis / placement routing timing verifications optimization (retiming) manual placement constraints limited versions for space implementation soft IPs: - libraries of soft IPs: communication protocols computing modules (filters, EDAC, compressor, PID, FFT) microprocessor core package technology easy to use - package technology easy to use (QFP) 1/ Introduction - 2/ EREMS presentation - 3/ Choice of FPGA target - 4/ Prototypes - 5/ Design - 6/ Performance - 7/ Programming - 8/ Conclusion

11 18 th September 2014 11 ● ESA– Mr. David Merodio Codinachs ● CNES– Mr. David Dangla SPECIAL THANKS TO

12 18 th September 2014 12 EREMS CONTACTS ● Gérard Dejonghe ● Nicolas Poiraudeau Chief Executive Officer Head of FPGA Department Email : gerard.dejonghe@erems.fr Email : nicolas.poiraudeau@erems.fr Phone: +33 - 5 61 36 06 06 www.erems.fr

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