1. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Physical creation of passive integrated components Layout and photo-micrograph of 1.5 micron CMOS elements Integrated Inductor Integrated Poly-Poly Capacitor

2. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Major focus on specific capacitance and inductance values Differs from parasitic capacitance and inductance which abound on-chip Capacitance Inductance Uses of Passive Integrated Elements DC block, AC coupling, AC bypass Filtering, Matching DC biasing Filtering, Matching

3. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Uses of Passive Integrated Elements: Examples Cascode LNA with Matching MOS VCO (C4 and C5 VVC)

4. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Capacitors in MOS

5. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitance generated from conductor overlays Most used overlay: metal-metal and poly- poly Basic structure based on parallel plate capacitance (neglects fringing) Capacitors

6. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors C a – capacitance per unit area: aF/  m 2 Typical values 1.0 pF capacitor

7. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Layer Tradeoffs P-P: higher capacitance per unit area, higher sheet resistance M-M; lower capacitance per unit area, lower sheet resistance Impacts Equivalent Circuit Capacitors

8. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors R1, R2: plate/layer losses C1: desired capacitance C2, C3: parasitic capacitance (top/bottom plate) R3, R4, C4, C5: substrate losses Metal-metal Poly-poly

9. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors R1, R2: plate/layer losses C1: desired capacitance C2, C3: parasitic capacitance (C3 > C2) R3, R4, C4, C5: substrate losses

10. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors R1, R2: plate/layer losses C1: desired capacitance C2, C3: parasitic capacitance (C2 > C3) R3, R4, C4, C5: substrate losses

11. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Design and determine the equivalent circuit (neglecting substrate effects) of a 2.8pF poly-poly capacitor with 50 micron overlap on each side. Capacitors: An Example

12. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Capacitors in MOS: Simulation and Experimental Results

13. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Example: Metal2-Metal1 floating capacitor Capacitors Technology: 1.5 micron CMOS Area: 105 by 64 microns RF wafer probing Frequency Range: 0.5 - 2.4 GHz

14. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Numerical Simulation Results Metal 2 Layer Metal 1 Layer

15. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Poly-poly floating capacitor Capacitors Technology: 1.5 micron CMOS Area: 78 by 64 microns RF wafer probing Contacts de-embedded Frequency Range: 0.5 - 2.4 GHz Series Capacitor Target: 2.8 pF

16. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Numerical Simulation Results Metal 2 Poly2 Poly 1 S 21 S 11

17. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Simplified capacitor model Measured S-parameter data Target Design Measured Equivalent Circuit C1: 2.8 pFC1: 2.84 pF, R1, R2=26, 24 Ohms Resulting C2: 0.18pF/0.18pF C2/C3: 0.02pF/ 0.387pF Experimental Results

18. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors in MOS

19. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors Figure of Merit for Inductor Integrated inductors suffer from low Q (4-10) L doesn’t scale like FET Traditional RF circuits have several inductors Self-resonance: Q=0

20. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors: Design Equations d out d in Parasitic capacitance and resistance important for element Q and resonant frequency Moran

21. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors: Design Equations d out d in Parasitic Capacitance Parasitic Resistance Length, width, spacing contribute to overall inductor frequency response.

22. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Equivalent Circuit Model L: desired inductance R1: conductive layer loss C1, C2: parasitic layer capacitance R2, R3, C3, C4: substrate losses Use top-most metal layer for the majority of the inductor for reduced parasitics

23. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductor: Design Example 150  m 250  m N=7.5 1.5 micron CMOS Inductor

24. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors: Design Example 150  m 250  m N=7.5

25. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Numerical Simulation Results Metal 2 Layer Metal 1 Layer

26. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Measured Results: Comparison

27. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. 2-level metal inductor with plain substrate Inductor Measurements Technology: 1.5 micron CMOS Area: 78 by 64 microns RF wafer probing Contacts de-embedded Frequency Range: 0.5 - 2.4 GHz

28. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Simplified inductor model S-parameter data Design ParametersMeasured Parameters Inductor Measurements

29. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Simplified inductor model Design ParametersComputed Parameters Inductor Measurements 900 MHz Results R = 26 Ohms L = 6.1 nH

30. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Advanced Modeling Substrate Effects Two substrate effects Substrate losses (Rsub, Csub) Substrate Coupling (Rcoup, Ccoup)

31. Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Bibliography “A simple wideband on-chip inductor model for silicon-based RF ICs”, J. Gil and H. Shin, IEEE MTT-51(9), p 2023, 2003. S. S. Mohan, et al., “Simple Accurate Expressions for Planar Spiral Inductances”, IEEE Journal of Solid-State Circuits, October 1999, pp. 1419- 1424. B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River, NJ, 1998. Y. Chu, H. Chuang, “A fully integrated 5.8 GHz U-NII band 0.18  m CMOS VCO”, IEEE Micro. Wireless Components Lett., vol. 13(7), p. 287, 2003.