1. August 24, 2011IDAP Kick-off meeting - TileCal ATLAS TileCal Upgrade LHC and ATLAS current status LHC designed for 10 34 cm -2 s -1 @ 7+7 TeV Limited to 3.5+3.5 TeV due to magnet problems – otherwise runs well Should reach 10 34 cm -2 s -1 and 7+7 TeV (6.5+6.5 TeV) after two years of magnet consolidation ATLAS also runs well – some consolidation needed Why upgrade? Adapt to improved LHC luminosity – factor 10 possible Adapt to changing physics requirements Remember that much must be replaced anyway due to old age and radiation damage

2. August 24, 2011IDAP Kick-off meeting - TileCal Phase 0 Phase 1Phase 2 LS3 Installation of sLHC hardware Current (not yet approved)upgrade upgrade schedule

3. August 24, 2011IDAP Kick-off meeting - TileCal Higher luminosity  more events accepted with current criteria but level 1 rate stays ~ 100kHz – L2 capacity increased but also event sizes Higher threshold not the answer  better L1 trigger decisions needed Better information - Better algorithms – Better architecture Move down algorithms in trigger hierarchy: EF  L2  L1(  L0) Higher luminosity  increased occupancy - ~200 minimum bias events/BC  pile up ID need replacement due to radiation damage and aging Calorimeter on-detector electronics designed for 10 year of 10 34 cm -2 s -1 FCAL replacement – radiation damage Muon fake reduction – cavern background – multiple scattering What are the main issues?

4. August 24, 2011IDAP Kick-off meeting - TileCal ATLAS Tile Calorimeter digitizer Major project Our work included:  Developing the concept  Several prototype runs  Test beam running  >2000 boards produced, tested, installed and commissioned Summation of analog outputs to form trigger data - send to L1 trigger Store data in digitizer until L1 response Send accepted data to DAQ

5. August 24, 2011IDAP Kick-off meeting - TileCal Data bandwidth of entire TileCal with 1024 independent drawer modules --> 50Tbps with duplication for redundancy  High speed parallel fiber optical transceiver (e.g. 12 fibers @ 5Gbps) Off-detectorOn-detector The main components of an upgraded drawer are:  New front-End boards – three alternative designs (3-in-1, FE-ASIC, QIE)  MainBoards – digitizing the FE signals  Processing Daughter Board – processing and high speed communication  New PMT dividers – new HVPS – new LVPS Off-detector - sROD modules TileCal Phase 2 Upgrade (full digital readout)

6. August 24, 2011IDAP Kick-off meeting - TileCal 4-fold redundancy – all fibers duplicated and 2 channels (on different fibers) per cell Clock, Trigger and Control are obtained via the GBT protocol Early prototypes are being developed (FE-board agnostic) Drawer Readout TileCal Phase 2 Upgrade

7. August 24, 2011IDAP Kick-off meeting - TileCal The Demonstrator project aims at a coordinated yet independent installation of digital trigger data links in a limited area of both LAr and TileCal during 2013-2014. The new data path should operate in parallel with analog trigger data path thus be compatible with the present trigger and readout The Calorimeter Readout Demonstrator Project

8. August 24, 2011IDAP Kick-off meeting - TileCal The plan is to develop a hybrid demonstrator drawer compatible with the present system aiming at evaluation in TileCal test facilities before the end of 2013 and then insertion of one hybrid drawer in ATLAS in the end of LS1 (i.e. mid 2014) Providing analog readout via present summation boards Firmware in the sROD module interfaces the TTC inputs and the ROD outputs Off-detectorOn-detector A TileCal hybrid drawer design

9. August 24, 2011IDAP Kick-off meeting - TileCal PC Adapter- board ADC HiTechGlobal FPGA board Off detector electronics ML605 On detector logic 3-in-1 FE board ATCA 100 m fiber PCI-e DAQ TTC DAQ and TTC not yet implemented A system slice model was assembled for developing firmware for the TileCal upgrade using a combination of dedicated hardware and of the shelf FPGA modules. This allows developing firmware and also software in parallel with the hardware instead of doing it after the hardware development is finished. The aim is to gradually replace the model parts with prototype solutions and later with production parts while adapting the firmware successively to the updated hardware. This will also help to provide test procedures for the evolving system The off detector clock drives the on-detector Electronics Data transfer via GBT A hybrid system test design

10. August 24, 2011IDAP Kick-off meeting - TileCal Gigabit Transceiver project (GBT) CERN developed transmission link intended as a successor to the current TTC system (Timing, Trigger and Control) used by all LHC experiments Will transmit data and control commands between detector and control room, as well as timing and triggers. We are contributing significantly to the GBT project  Have so far improved latency performance by a factor of 3 in the FPGA implementation of GBT.

11. August 24, 2011IDAP Kick-off meeting - TileCal Design tools used xxx