1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Parade of Flip-Flops CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff Homework 8 is due today

4. Review Lecture

5. A simple memory element with NOT Gates x x x

6. A simple memory element with NAND Gates x x x

7. A simple memory element with NOR Gates x x x

8. Basic Latch

9. A simple memory element with NOR Gates

11. ResetSet

12. Reset SetQ [ Figure 5.3 from the textbook ] A memory element with NOR gates

13. [ Figure 5.3 & 5.4 from the textbook ] Two Different Ways to Draw the Same Circuit

14. SRQ a Q b 00 01 10 11 0/1 1/0 01 10 00 (a) Circuit(b) Truth table Q a Q b R S (no change) SR Latch: Circuit and Truth Table [ Figure 5.4a,b from the textbook ] x1x1 x2x2 f 001 010 100 110 NOR Gate NOR Gate Truth table (Undesirable)

15. Gated SR Latch

16. [ Figure 5.5a from the textbook ] Circuit Diagram for the Gated SR Latch

17. This is the “gate” of the gated latch

18. Circuit Diagram for the Gated SR Latch Notice that these are complements of each other

19. [ Figure 5.5 from the textbook ] Gated SR Latch: Circuit Diagram, Characteristic Table, and Graphical Symbol (Undesirable)

20. S R Clk Q Q [ Figure 5.6 from the textbook ] Gated SR latch with NAND gates

21. S R Clk Q Q Gated SR latch with NAND gates In this case the “gate” is constructed using NAND gates! Not AND gates.

22. S R Clk Q Q Gated SR latch with NAND gates Also, notice that the positions of S and R are now swapped.

23. S R Clk = 1 Q Q Gated SR latch with NAND gates S R Finally, notice that when Clk=1 this turns into the basic latch with NAND gates, i.e., the SR Latch. 1 1

24. S R Clk Q Q Gated SR latch with NOR gates Gated SR latch with NAND gates

25. S R Clk Q Q Gated SR latch with NOR gates Gated SR latch with NAND gates Graphical symbols are the same

26. S R Clk Q Q Gated SR latch with NOR gates Gated SR latch with NAND gates Characteristic tables are the same (undesirable)

27. Gated D Latch

28. [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch

29. [ Figure 5.7a,b from the textbook ] Gated D Latch: Circuit Diagram, Characteristic Table, and Graphical Symbol Note that it is now impossible to have S=R=1. When Clk=1 the output follows the D input. When Clk=0 the output cannot be changed.

30. t su t h Clk D Q [ Figure 5.8 from the textbook ] Setup and hold times for Gated D latch Setup time (t su ) – the minimum time that the D signal must be stable prior to the the negative edge of the Clock signal Hold time (t h ) – the minimum time that the D signal must remain stable after the the negative edge of the Clock signal

31. Master-Slave D Flip-Flop

32. Constructing a Master-Slave D Flip-Flop From Two D Latches MasterSlave

33. Constructing a Master-Slave D Flip-Flop From Two D Latches MasterSlave

34. Constructing a Master-Slave D Flip-Flop From Two D Latches MasterSlave

35. Constructing a Master-Slave D Flip-Flop From Two D Latches [ Figure 5.9a from the textbook ]

36. Constructing a Master-Slave D Flip-Flop From one D Latch and one Gated SR Latch (This version uses one less NOT gate) MasterSlave

37. Constructing a Master-Slave D Flip-Flop From one D Latch and one Gated SR Latch (This version uses one less NOT gate) MasterSlave

38. Edge-Triggered D Flip-Flops

39. (a) Circuit D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk [ Figure 5.9a from the textbook ] Master-Slave D Flip-Flop

40. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk

41. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk

42. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk D Q Q D Q Q

43. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements

44. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements Level-sensitive (the output mirrors the D input when Clk=1)

45. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements Positive-edge-triggered

46. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements Negative-edge-triggered

47. [ Figure 5.14 from the textbook ] Flip-Flop Timing Parameters Setup time Hold time clock-to-Q propagation delay

48. T Flip-Flop

49. [ Figure 5.15a from the textbook ] T Flip-Flop

50. [ Figure 5.15a from the textbook ] T Flip-Flop Positive-edge-triggered D Flip-Flop

51. [ Figure 5.15a from the textbook ] T Flip-Flop What is this?

52. Q Q T D

53. Q Q T D += ?

54. T 0 1 D Q Q Clock T Flip-Flop

55. What is this? += ?

56. T D Q Q Clock T Flip-Flop

57. [ Figure 5.15a-c from the textbook ] T Flip-Flop (circuit, truth table and graphical symbol)

58. T Flip-Flop (How it Works) If T=0 then it stays in its current state If T=1 then it reverses its current state In other words the circuit “toggles” its state when T=1. This is why it is called T flip-flop.

59. JK Flip-Flop

60. [ Figure 5.16a from the textbook ] JK Flip-Flop D = JQ + KQ

61. [ Figure 5.16 from the textbook ] JK Flip-Flop JQ Q K 0 1 Qt1+  Qt  0 (b) Truth table(c) Graphical symbol J 0 0 0 1 1 1 Qt  1 K D Q Q Q Q J Clock (a) Circuit K

62. JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop

63. Questions?

64. THE END