1. CHAPTER 14 Digital Systems

2. Figure 14.1 RS flip-flop symbol and truth table Figure 14.1 14-1

3. Timing diagram for the RS flip-flop Figure 14.2 14-2

4. Figure 14.4 The RS flip-flop with enable, preset, and clear lines: (a) logic diagram, (b) timing diagram, (c) IC schematic Figure 14.4 14-3

5. Figure 14.5 Data latch and associated timing diagram Figure 14.5 14-4

6. Figure 14.6 The D flip-flop: (a) functional diagram, (b) symbol, (c) timing waveforms, and (d) IC schematic Figure 14.6 14-5

7. Figure 14.7 The JK flip-flop: (a) functional diagram, (b) device symbol, and (c) IC schematic Figure 14.7 14-6

8. Truth table for the JK flip-flop Figure 14.8 14-7 Figure 14.8

9. Figure 14.10 Binary up counter functional representation, state table, and timing waveforms Figure 14.10 14-8

10. Figure 14.11 Decade counter: (a) counting sequence; (b) functional diagram; and (c) IC schematic Figure 14.11 14-9

11. Figure 14.12 Ripple counter Figure 14.12 14-10

12. Figure 14.16 Three-bit synchronous counter Figure 14.16 14-11

13. Figure 14.17 Ring counter Figure 14.17 14-12

14. Figure 14.22 A 4-bit parallel register Figure 14.22 14-13

15. A 4-bit shift register Figure 14.23 14-14

16. Figure 14.26 A 3-bit binary counter and state diagram Figure 14.26 14-17

17. Table 14.5 14-18 State transition table for modulo-4 up-down counter

18. State diagram of a modulo-4 up-down counter Figure 14.27 14-19

19. Figure 14.28 14-20 Karnaugh maps for flip-flop inputs in modulo-4 counter

20. Implementation of modulo-4 counter Figure 14.29 14-21

21. Figure 14.30 14-22 Structure of a digital data acquisition and control system

22. (a) High-level block diagram of microcontroller; (b) internal organization of microcontroller Figure 14.33 14-23