1. CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flop with Additional Inputs 11.9Summary Problems

2. Spring 2004Digital System2 Objectives 1.Explain in words the operation of S-R and gated D latches 2. Explain in words the operation of D, D-CE, S-R, J-K and T flip-flops 3. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals 4. Draw a timing diagram relating the input and output of such latches flip-flops 5. Show how latches and flip-flops can be constructed using gates. Analyze the operation of a flip-flop that is constructed of gates and latches

3. Spring 2004Digital System3 Flip-Flops (FF) Sequential switching networks output depends on both present inputs and past sequence of inputs Flip-Flops are most commonly used memory devices Flip-Flops assume one of two stable output states has one or more inputs which can cause the output state to change

4. Spring 2004Digital System4 Feedback output of one gate is connected back into the another gate's input so as to form a closed loop needed to construct a switching circuit which has a memory Inverter with feedback oscillate back and forth between 0 and 1 never reach a stable condition oscillation rate is determined by the inverter's propagation delay

5. Spring 2004Digital System5 11.1Introduction Fig 11-2.  Stable state Two inverters with feedback two stable conditions – stable states

6. Spring 2004Digital System6 S-R(Set-Reset) Flip-Flop can make a simple F/F by using a feedback Operations : S=R=0, Q=0, P=1? stable? yes becomes S=1 S=1, R=0 P=0, Q=1 S=0 again. Then? P=0, Q=1 R=1 – Q=0, P=1 R=0 : go back to first Two different stable state for a given set of inputs R=S=1 을 허용하지 않으면 항상 P=Q’

7. Spring 2004Digital System7 SR F/F : cross-coupled structure To emphasize the symmetry, SR F/F is often drawn in cross-coupled form Q 가 R 이 입력인 NOR gate 의 출력이지만 기호는 Fig 11-5 처럼 사용 S-R latch

8. Spring 2004Digital System8 Improper Operation What if S=R=1? P=Q=0 violate basic F/F rules (F/F outputs to be complements) oscillate if the gate delays are exactly equal

9. Spring 2004Digital System9 11.2 Set-Reset Latch Fig 11-7. Timing Diagram for S-R Latch Table 11-1. S-R Latch Operation 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 010011--010011-- Inputs not allowed ε : response time or delay time of the latch S R Q + 0 0 Q 0 1 0  1 0 1 1 1 -

10. Spring 2004Digital System10 11.2 Set-Reset Latch Fig 11-8. Map for next-state equation or characteristic equation

11. Spring 2004Digital System11 Switch Debouncing with an S-R Latch

12. Spring 2004Digital System12 11.2 Set-Reset Latch Fig 11-10. - Latch 1 1 0 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 010011--010011-- Inputs not allowed

13. Spring 2004Digital System13 11.3 Gated D Latch Figure 11-11. Gated D Latch Figure 11-12. Symbol and Truth Table for Gated Latch 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0101001101010011

14. Spring 2004Digital System14 11.4 Edge-Triggered D Flip-Flop Figure 11-13. D Flip-Flops 0 0 1 1 0 1 00110011 Truth table Figure 11-14. Timing for D Flip-Flop (Falling-Edge Trigger)

15. Spring 2004Digital System15 11.4 Edge-Triggered D Flip-Flop Given FunctionFigure 11-15. D Flip-Flop (Rising-Edge Trigger) Figure 11-16. Setup and Hold Times for an Edge-Triggered D Flip-Flop

16. Spring 2004Digital System16 11.4 Edge-Triggered D Flip-Flop Figure 11-17. Determination of Minimum Clock Period

17. Spring 2004Digital System17 11.5 S-R Flip-Flop Figure 11-18. S-R Flip-Flop Operation summary : S=R=0 S=1, R=0 S=0, R=1 S=R=1 No state change Set Q to 1 (after active Ck edge) Reset Q to 0 (after active Ck edge) Not allowed Figure 11-19. S-R Flip-Flop Implementation and Timing

18. Spring 2004Digital System18 11.6 J-K Flip-Flop Figure 11-20. J-K Flip-Flop (Q Changes on the Rising Edge) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0100111001001110 Truth table and characteristic equation

19. Spring 2004Digital System19 11.6 J-K Flip-Flop Figure 11-21. Master-Slave J-K Flip-Flop (Q Changes on Rising Edge)

20. Spring 2004Digital System20 11.7 T Flip-Flop Figure 11-22. T Flip-Flop 0 0 1 1 0 1 01100110 Figure 11-23. Timing Diagram for T Flip-Flop (Falling-Edge Trigger)

21. Spring 2004Digital System21 11.7 T Flip-Flop Figure 11-24. Implementation of T Flip-Flop

22. Spring 2004Digital System22 11.8 Flip-Flops with Additional Inputs Figure 11-25. D Flip-Flop with Clear and Preset x x 0 0 x x 0 1 x x 1 0 0 1 1 1 1 1 0,1, x 1 1 (not allowed) 1 0 1 Q(no change) Figure 11-26. Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset

23. Spring 2004Digital System23 11.8 Flip-Flops with Additional Inputs Figure 11-27. D Flip-Flop with Clock Enable The MUX output : The characteristic equation :

24. Spring 2004Digital System24 11.9 Summary (S-R latch or flip-flop) (gated D latch) (D flip-flop) (D-CE flip-flop) (J-K flip-flop) (T flip-flop)