1. Gates Winkler Jordan Samuel Fei Yin Shen September 21, 2009 Virtual Wallet Proposed chip architecture To create a handheld device which will save money and time through budget assistance and improve the shopping experience.

2. Status Finished Flow Chart Arithmetic Verilog FSM Verilog Transistor Estimate Floor Plan To Do Schematic Layout Controller Verlog Testing

3. Block Diagram Item SRAM Adder Subtractor ComparatorBudget FSM USER ID Discount FSM RFID keypad SecureOne card Display SecureOne Database SecureOne Store Database Input FSM Multiply Divide Checks RFID tag against store database to get price etc. x1000 /1000 Interfacing logic for Database and Display Budget Reg Total Reg Add_price 30 bit sub_price 30 bit total_reg 30 bit Going_out 30 bitTotal_out 20 bit ID 8 bit Enough 1 bit Budget 30 bit Going in 20 bit Budg_in 20 bit Enough 1 bit, Remove 1 bit Over_warnign 1 bit, Over 1 bit, Budget 30 bit ID 8 bit

4. Flow Chart Insert Card Swipe Item – Remove Item Checkout

5. Startup – Insert Card First the user inserts her SecureOne card. The input FSM is signaled to ask for a budget on the display. The user’s information and accounts are looked up in a secure online data base. USER IDSecureOne card Display Input FSM SecureOne Database 16 bit

6. Startup – Input Budget USER ID Input FSM SecureOne Database The user then inputs a budget as well as the account they wish to use. The user’s account is checked to see if they have enough money in their account to cover the budget. If not the User is prompted to input another budget. If they have enough then it continues to the next step. keypad Other Logic Budget 20 bit

7. Startup – Don’t Input Budget USER ID Input FSM SecureOne Database The user also has the option to not input a budget. If they chose to do so the maximum value in their account is passed into the next step. If the maximum in their account exceeds the maximum allowed by the bit- length then the maximum value allowed will be passed in (2 20 ÷1000) keypad Other Logic Budget Max 20 bit

8. Startup – Storing Budget Multiply x1000 Budget Reg Budget Input The Budget Value is then stored in a budget register. To make the math easier we multiply everything by 1000 at the start. -Do not need to deal with decimal points in arithmetic -Can grant more accurate discounts. The final result is stored in a Register. 20 bit

9. USER ID Input FSM SecureOne Database keypad Budget Max 20 bit Multiply x1000 Budget Reg 20 bit Changing Budget If at a later point the user want to change her budget she can She uses the keypad to signal that she wants to and types in her new budget. The Process then repeats itself.

10. Swipe an Item – Item Swiped When an item is swiped a few things happen. The item is stored in the Item SRAM The item is also passed into the discount FSM and the online database is consulted. 8 bit Item SRAM RFID Discount FSM SecureOne Database

11. Swipe an Item – Item Swiped The item’s value is looked up in a store database and then passed to the adder. There is a Total Register which stores the value of all the items the user currently wants to buy. It’s initial value is 0 and it resets to 0 when the user is done shopping. The adder takes the value from Total Register and adds the value of the item to it. The new value is stored back into the Total Reg Item SRAM Adder Store Database Total Reg 20 bit

12. Swipe an Item – Discount Certain users might be granted discounts. When an item is swiped the secure data base is checked for a discount. If one is found the Discount FSM passes it into the Subtractor which subtracts it from the value stored in Total Reg. The new Value is stored back into Total Reg. Subtractor SecureOne Database Total Reg Discount FSM 20 bit USER ID

13. Item SRAM Adder Subtractor USER ID RFID SecureOne Database Store Database Total Reg Discount FSM 8 bit 20 bit Swipe an Item – Recap

14. Swipe an Item – Is it Over? After the total value of the items is determined the value in Total Reg is passed into the Comparator. The value is compared to the value in the Budget Register. The correct signal is passed into the budget FSM. ComparatorBudget FSM Budget Reg Total Reg Over Budget? 20 bit 1 bit

15. Swipe an Item – To the Display ComparatorBudget FSM Display Divide /1000 Budget Reg Total Reg The value in Total Reg is also passed to the Divide block which will bring the value back down to dollars and cents. The result is sent to the display. The budget FSM also sends a message to the display reporting whether or not the user has gone over budget. Over Budget? 20 bit 1 bit

16. Remove an Item At any time the user wants she will have the option to remove an item. She signals she wants to do this with the keypad which is sent to the Budget FSM. A list of items is then sent to the display from the item SRAM. Item SRAM keypad DisplayBudget FSM

17. Remove an Item The user then uses the keypad to select an item to remove. It’s value is looked up in the online database and sent to the Subtractor. The Subtractor subtracts the value from Total Reg. Item is either removed from the SRAM or marked as removed. Item SRAM Subtractor keypad Total Reg Store Database 20 bit

18. Item SRAM Subtractor Budget FSM keypad Display Total Reg Store Database Remove an Item - Recap 20 bit

19. Checkout – Start Checkout USER ID SecureOne Database Arithmetic Logic When the user decides she wants to checkout she uses the Keypad to signal that she’s ready. If the current total is less than the budget then the amount is deducted from her online account. If the current amount is greater than the budget then the user will be asked if she wants to checkout anyway or remove items till she is under the budget. If the current amount is greater than the money in her account then the user will be informed that she must remove items till she is within an allowable amount.

20. Flow Final Once the user is checked out and card is removed system resets – Total Register and Budget Register are reset to 0 – SRAM and User ID cleared If user finishes without checking out system resets when card is removed

21. Low Battery FSM Good Battery Low Battery Battery Good Battery Low Battery Charging When Plugged in Battery Starts Charging and returns to the correct State when unplugged Battery is Good. Works normally and a green light is displayed Battery is getting low. A message to either finish and checkout or switch machines is displayed. Battery is critically low. Can no longer guarantee safe transactions. Machine gives a final warning before automatically shutting off, clearing data and disconnecting from SecureOne to protect private information.

22. SRAM Plan When we delete an item the memory space in the SRAM is reset and is now eligible for writing to. We will use our old 322 SRAM design. – 2 read 1 write SRAM – Address decoder is used to select wordline – Bitline reset function will be used to reset a wordline when an item is removed.

23. Verilog Arithmetic Add Subtract Multiply Divide Compare

24. Verilog Arithmetic module adder(A, B, Z); output [20:0] Z; input [20:0] A; input [20:0] B; assign {Z} = A+B; endmodule module subtract(A, B, Z); output [20:0] Z; input [20:0] A; input [20:0] B; assign {Z} = A-B; endmodule module multiply (A, Z); output [20:0] Z; input [20:0] A; assign {Z} = A*1000; endmodule module divide (A, Z); output [20:0] Z; input [20:0] A; assign {Z} = A/1000; endmodule module comparator (A, B, Z); output reg [20:0] Z; input [20:0] A; input [20:0] B; always @* begin if(A>B) begin Z <= 1; end else begin Z <= 0; end endmodule

25. Verilog Arithmetic Testbench results: # Loading work.test_add # Loading work.adder # run -all ; quit # adder tests # A= 5 + B= 7 = Z= 12 # # ** Note: $finish : arithmatic.v(70) # Time: 1 us Iteration: 0 Instance: /test_add # Loading work.test_sub # Loading work.subtract # run -all ; quit # subtract tests # A= 150069 - B= 22 = Z= 150047 # # ** Note: $finish : arithmatic.v(93) # Time: 1 us Iteration: 0 Instance: /test_sub # Loading work.test_multiply # Loading work.multiply # run -all ; quit # multiply tests # A= 5 x 1000 = Z= 5000 # # ** Note: $finish : arithmatic.v(115) # Time: 1 us Iteration: 0 Instance: /test_multiply # Loading work.test_divide # Loading work.divide # run -all ; quit # multiply tests # A= 670000 / 1000 = Z= 670 # # ** Note: $finish : arithmatic.v(137) # Time: 1 us Iteration: 0 Instance: /test_divide # Loading work.test_comp # Loading work.comparator # run -all ; quit # comparator tests # A= 5, B= 7 Z= 0 # # A= 400, B= 100 Z= 1 # # ** Note: $finish : arithmatic.v(164) # Time: 2 us Iteration: 0 Instance: /test_comp

26. Verilog FSM Psudeo Code: Follows this design: parameter [2:0] stateZero = 3'b000, stateOne = 3'b001, stateTwo = 3'b010, stateThree = 3'b011, stateFour = 3'b100; always @* begin case (state) stateZero: nextState = ( x==0 )? stateOne : stateZero; stateOne: nextState = ( x==0 )? stateTwo : stateZero; stateTwo: nextState = ( x==0 )? stateTwo : stateThree; stateThree: nextState = ( x==0 )? stateFour : stateZero; stateFour: nextState = ( x==0 )? stateTwo : stateZero; default: nextState = 3'b000; endcase end

27. Verilog FSM Testbench results: # Loading work.testInput # Loading work.InputFSM # run -all ; quit # 0 clk = 0, state=x, bug_sel=0, enough=0 # 10 clk = 1, state=0, bug_sel=0, enough=0 # 20 clk = 0, state=0, bug_sel=1, enough=0 # 30 clk = 1, state=1, bug_sel=1, enough=0 # 40 clk = 0, state=1, bug_sel=1, enough=0 # 50 clk = 1, state=2, bug_sel=1, enough=0 # 60 clk = 0, state=2, bug_sel=1, enough=0 # 70 clk = 1, state=0, bug_sel=1, enough=0 # 80 clk = 0, state=0, bug_sel=1, enough=1 # 90 clk = 1, state=1, bug_sel=1, enough=1 # 100 clk = 0, state=1, bug_sel=1, enough=1 # 110 clk = 1, state=2, bug_sel=1, enough=1 # 120 clk = 0, state=2, bug_sel=1, enough=1 # 130 clk = 1, state=3, bug_sel=1, enough=1 # ** Note: $finish : FSM.v(113) # Time: 131 ns Iteration: 0 Instance: /testInput # Loading work.testBudget # Loading work.BudgetFSM # run -all ; quit # 0 clk = 0, state=x, over=0, remove=0, checkout = 0 # 10 clk = 1, state=0, over=0, remove=0, checkout = 0 # 20 clk = 0, state=0, over=0, remove=0, checkout = 0 # 30 clk = 1, state=0, over=0, remove=0, checkout = 0 # 40 clk = 0, state=0, over=1, remove=0, checkout = 0 # 50 clk = 1, state=2, over=1, remove=0, checkout = 0 # 60 clk = 0, state=2, over=1, remove=0, checkout = 0 # 70 clk = 1, state=2, over=1, remove=0, checkout = 0 # 80 clk = 0, state=2, over=1, remove=1, checkout = 0 # 90 clk = 1, state=3, over=1, remove=1, checkout = 0 # 100 clk = 0, state=3, over=1, remove=1, checkout = 0 # 110 clk = 1, state=0, over=1, remove=1, checkout = 0 # 120 clk = 0, state=1, over=1, remove=1, checkout = 1 # 130 clk = 1, state=1, over=1, remove=1, checkout = 1 # ** Note: $finish : FSM.v(186) # Time: 131 ns Iteration: 0 Instance: /testBudget # Loading work.testDiscount # Loading work.DiscountFSM # run -all ; quit # 0 clk = 0, state=x, get=0, discount=0 # 10 clk = 1, state=0, get=0, discount=0 # 20 clk = 0, state=0, get=0, discount=0 # 30 clk = 1, state=0, get=0, discount=0 # 40 clk = 0, state=0, get=1, discount=0 # 50 clk = 1, state=1, get=1, discount=0 # 60 clk = 0, state=1, get=0, discount=0 # 70 clk = 1, state=0, get=0, discount=0 # 80 clk = 0, state=0, get=1, discount=0 # 90 clk = 1, state=1, get=1, discount=0 # 100 clk = 0, state=1, get=1, discount=1 # 110 clk = 1, state=2, get=1, discount=1 # ** Note: $finish : FSM.v(148) # Time: 111 ns Iteration: 0 Instance: /testDiscount

28. Verilog SRAM always @(posedge get) begin if (full == 1) begin array[stack_address] = In_ID; end else begin array[address] = In_ID; address = address +1; end always@(posedge remove) begin $display("In_ID = %d, array[search_add] = %d", In_ID, array[search_add]); while(array[search_add] != In_ID) begin $display("I'm in a loop!"); search_add = search_add +1; end if (array[search_add] == In_ID)begin address_out = search_add; end always@(posedge backup) begin for(search_add = 0; search_add <99; search_add = search_add +1) begin $display("for_loop"); Out_ID = array[search_add]; end search_add=0; end always @* begin if (address == 99) begin full = 1; end

29. Verilog SRAM Stack always@(posedge push or posedge pop) begin if (push == 1) begin if (empty ==1) begin Stack[SP] = address; empty = 0; end else begin SP = SP +1; Stack[SP] = address; end if (pop == 1) begin if ((SP == 0) && (empty !=1)) begin DataR = Stack[SP]; empty = 1; end else begin DataR = Stack[SP]; if(SP!=0) begin SP = SP-1; end

30. Verilog Top Module always@(posedge clk) begin counter = counter +1; end always@* begin if (in_state == 3'b11) begin assign going_in = budg_in; if (budg_state == 3'b10) begin assign over_warning = 1; end if (budg_state == 3'b01) begin assign going_out = total_reg; end if (batt_state == 3'b01) begin assign backup = 1; end if (counter == 15) begin assign backup = 1; assign counter = 0; end always@(price) begin if (budg_state == 3'b11 || disc_state == 3'b10) begin assign add_price = 0; #10 assign sub_price = price; if (sum > 0) begin total_reg = sum; sub_price = 0; end else begin assign sub_price = 0; #10 assign add_price = price; if (sum > 0) begin total_reg = sum; add_price = 0; end

31. Design Transistor Count Floor Plan Metal Direction Floor Plan

32. Transistor Count BlockTransistor SRAM5000 Adder500 Subtractor500 Multiply500 Divide500 Comparator500 Logic2000 Budget Register120 Total Register120 Total9740

33. Transistor Count(new) BlockTransistor SRAM5000 Adder720 (500) Subtractor780 (500) Multiply260 (500) Divide260 (500) Comparator900 (500) Logic600 (2000) Budget Register360 (120) Total Register360 (120) Total9240(9740)

34. Structure of implementation SRAM: 1bit~6transistors Adder: Ripple-carry adder, 1bit~24transistors Subtractor: A-B=A+ˉB, adder and inverter Multiply: left shift register Divide: right shift register Comparator: Magnitude comparator Register: each bit of register would be a latch, 1bit~12transistors Logic: Not decided

35. Size Estimation BlockArea (um^2) SRAM1688 Adder806 (840) Subtractor874 (840) Multiply8904 (840) DivideNot decided(840) Comparator1018 (840) LogicNot decided (3360) Budget Register404 (202) Total Register404 (202) TotalNot decided (9652)

36. Item SRAM 40*42 Total Reg 40*5.5 Comparator 40*21 Budget Reg 40*5.5 Adder 40*21 Subtractor 40*21 Divide 40*21 Multiply 40*21 Discount FSM 40*28 Budget FSM 40*28 Input FSM 40*28 RFID Store Database SecureOne Database Display SecureOne card USER ID keypad Floor Plan 30 1 20 8 8 16 20 30

37. M1, M2 – Local and global interconnects M3,M4 – Clock – Ground and VDD Metal 1Arbitrary Metal 2Arbitrary Metal 3 Vertical Metal 4 Horizontal Metal Direction (not decided)

38. Reference CMOS VLSI Design, A Circuit and Systems Perspective Neil H.E. Weste, David Harris