Presentation is loading. Please wait.

Presentation is loading. Please wait.

Fall 2006 1 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Computer Organization Lecture 16 Write-through, write-back cache Memory.

Published byAnastasia Curtis Modified over 8 years ago

Similar presentations

Presentation on theme: "Fall 2006 1 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Computer Organization Lecture 16 Write-through, write-back cache Memory."— Presentation transcript:

1 Fall 2006 1 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Computer Organization Lecture 16 Write-through, write-back cache Memory performance

2 Fall 2006 2 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Memory design goals Unlimited memory size –No upper bound on memory addresses –Not practical or possible: cost, implementation Infinite memory bandwidth –Zero latency memory accesses –Not practical or possible: cost, laws of physics Memory hierarchy can approximate goals

3 Fall 2006 3 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Principle of locality Programs access a relatively small portion of their address space at any instant of time Temporal locality: once memory is accessed, its likely to be accessed again (locality in time) Spatial locality: once a memory address is selected, its neighbors are likely to be selected (locality in space)

4 Fall 2006 4 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Memory hierarchy Memory closest to CPU is most expensive (fast) but smallest On-chip On-board In-system

5 Fall 2006 5 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Four cache cases Read –Hit –Miss Write –Hit –Miss NOTE: hit rate + miss rate = 1.0

6 Fall 2006 6 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Cache reads Hit –Data from cache sent to CPU –Access time very fast Miss –Data from memory sent to CPU –Data also written into cache –Tag bits written to tag memory –Access time slow

7 Fall 2006 7 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Cache writes Data from CPU written to cache Tag bits of address written to cache tag memory Data from CPU written to memory (write- through) Valid bit set

8 Fall 2006 8 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Another look at writes Write-through –All writes update memory and cache –Simple, less expensive, slow Write-back –A write updates cache only (inconsistency) –Memory updated only for write miss to modified cache (miss modified) –Faster, more expensive

9 Fall 2006 9 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Write back cache Modified blocks must update (WB) memory Index TagData V 000 001 010 011 100 101 110 111 Y N Y Y N N Y N 000 N 10 Mem (10110) Y 11 Mem (11010) N 10 Mem (10000) Y 00 Mem (00011) M N 11 Mem (11000) No write back N 10 Mem (10010) Write back N 01 Mem (01011) Write back N 01 Mem (01110) No write back

10 Fall 2006 10 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Write-back? Cache memory indexVMtagdata 000YY100x123 001NY110x456 010NN010x789 011YY000xabc 100YN010xdef 101YY110x123 110YY100x456 111NY000x789 CPU write adrhit?WB? 1 0001 1 1101 0 0011 1 0000 0 1110 0 0000 0 1111

11 Fall 2006 11 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Direct-mapped example Bits 0 & 1 address data bytes Lower 10 bits address cache Upper 20 bits compared to tag bits Cache size is 1K words or 4KB Block size is 32-bits or one word

12 Fall 2006 12 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Memory performance Metrics: latency L in ns, bandwidth B = 1/L in B/s Average latency, L ave Assumes cache latency same for reads and writes Expression may be applied recursively

13 Fall 2006 13 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Find average latency? Direct mapped, write-through cache CPU clocked at 1.5 GHz DDR memory speed is 500 MHz Cache cycle time is 100 ps Hit rate is 0.95 One write to every three reads

14 Fall 2006 14 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Set associative cache Add more direct- mapped caches Two, four, eight- way common Data may reside in any set set 0set 1 set 2 set 3

15 Fall 2006 15 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Set associative design Must determine which set to use/replace upon cache miss Possible algorithms –Least recently used (LRU): most common –Random: good performance –First-in, first-out: FIFO

16 Fall 2006 16 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS and MDP16 Architecture comparison

17 Fall 2006 17 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS PC PC

18 Fall 2006 18 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 PC?

19 Fall 2006 19 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS mux/memory Mem

20 Fall 2006 20 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 mux/memory?

21 Fall 2006 21 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS IR IR

22 Fall 2006 22 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 IR?

23 Fall 2006 23 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS MDR MDR

24 Fall 2006 24 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 MDR?

25 Fall 2006 25 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS mux/Reg/A&B Reg

26 Fall 2006 26 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 mux/Reg/A&B?

27 Fall 2006 27 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS mux’s/ALU ALU

28 Fall 2006 28 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 mux’s/ALU

29 Fall 2006 29 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS PCsrc PCsrc

30 Fall 2006 30 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 PCsrc?

31 Fall 2006 31 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MIPS Controller Control

32 Fall 2006 32 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 controller

33 Fall 2006 33 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering

34 Fall 2006 34 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Write-back? Cache memory indexVMtagdata 000YY100x123 001NY110x456 010NN010x789 011YY000xabc 100YN010xdef 101YY110x123 110YY100x456 111NY000x789 CPU write adrhit?WB? 1 0001nn 1 1101yn 0 0011yn 0 0010nn 1 0100nn 0 1110ny 0 0000ny 0 1111nn

35 Fall 2006 35 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Find average latency? Answer should be less then memory speed

36 Fall 2006 36 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 PC ? PC

37 Fall 2006 37 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 mux/memory? mux/mem

38 Fall 2006 38 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 IR ? IR

39 Fall 2006 39 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 MDR ? MDR

40 Fall 2006 40 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 mux/Reg/A&B ? Reg

41 Fall 2006 41 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 mux’s/ALU ? ALU

42 Fall 2006 42 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 PCsrc ? PCsrc

43 Fall 2006 43 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering MDP16 Controller ? Control

44 Fall 2006 44 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering

45 Fall 2006 45 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering

46 Fall 2006 46 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering

Download ppt "Fall 2006 1 EE 333 Lillevik 333f06-l16 University of Portland School of Engineering Computer Organization Lecture 16 Write-through, write-back cache Memory."

Similar presentations

Lecture 19: Cache Basics Today’s topics: Out-of-order execution

Lecture 19: Cache Basics Today’s topics: Out-of-order execution
1 Lecture 13: Cache and Virtual Memroy Review Cache optimization approaches, cache miss classification, Adapted from UCB CS252 S01.

1 Lecture 13: Cache and Virtual Memroy Review Cache optimization approaches, cache miss classification, Adapted from UCB CS252 S01.
Lecture 8: Memory Hierarchy Cache Performance Kai Bu

Lecture 8: Memory Hierarchy Cache Performance Kai Bu
Fall 2005 1 EE 333 Lillevik480f05-a3 University of Portland School of Engineering EE 333 Final Exam December 15, 2005 Instructions 1.Print your name, student.

Fall EE 333 Lillevik480f05-a3 University of Portland School of Engineering EE 333 Final Exam December 15, 2005 Instructions 1.Print your name, student.
Fall 2005 1 EE 333 Lillevik480f05-a2 University of Portland School of Engineering EE 333 Exam 2 November 10, 2005 Instructions 1.Print your name, student.

Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering EE 333 Exam 2 November 10, 2005 Instructions 1.Print your name, student.
Fall 2006 1 EE 333 Lillevik333f06-e2 University of Portland School of Engineering EE 333 Exam 2 November 9, 2006 Instructions 1.Print your name, student.

Fall EE 333 Lillevik333f06-e2 University of Portland School of Engineering EE 333 Exam 2 November 9, 2006 Instructions 1.Print your name, student.
1 The Memory Hierarchy Ideally one would desire an indefinitely large memory capacity such that any particular word would be immediately available … We.

1 The Memory Hierarchy Ideally one would desire an indefinitely large memory capacity such that any particular word would be immediately available … We.
1 Recap: Memory Hierarchy. 2 Memory Hierarchy - the Big Picture Problem: memory is too slow and or too small Solution: memory hierarchy Fastest Slowest.

1 Recap: Memory Hierarchy. 2 Memory Hierarchy - the Big Picture Problem: memory is too slow and or too small Solution: memory hierarchy Fastest Slowest.
Cache Memory Locality of reference: It is observed that when a program refers to memory, the access to memory for data as well as code are confined to.

Cache Memory Locality of reference: It is observed that when a program refers to memory, the access to memory for data as well as code are confined to.
CSC 4250 Computer Architectures December 8, 2006 Chapter 5. Memory Hierarchy.

CSC 4250 Computer Architectures December 8, 2006 Chapter 5. Memory Hierarchy.
July 2005Computer Architecture, Memory System DesignSlide 1 Part V Memory System Design.

July 2005Computer Architecture, Memory System DesignSlide 1 Part V Memory System Design.
1 Copyright © 2012, Elsevier Inc. All rights reserved. Chapter 2 (and Appendix B) Memory Hierarchy Design Computer Architecture A Quantitative Approach,

1 Copyright © 2012, Elsevier Inc. All rights reserved. Chapter 2 (and Appendix B) Memory Hierarchy Design Computer Architecture A Quantitative Approach,
1  1998 Morgan Kaufmann Publishers Chapter Seven Large and Fast: Exploiting Memory Hierarchy.

1  1998 Morgan Kaufmann Publishers Chapter Seven Large and Fast: Exploiting Memory Hierarchy.
Cache Memory Adapted from lectures notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley.

Cache Memory Adapted from lectures notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley.
1 COMP 206: Computer Architecture and Implementation Montek Singh Mon, Oct 31, 2005 Topic: Memory Hierarchy Design (HP3 Ch. 5) (Caches, Main Memory and.

1 COMP 206: Computer Architecture and Implementation Montek Singh Mon, Oct 31, 2005 Topic: Memory Hierarchy Design (HP3 Ch. 5) (Caches, Main Memory and.
Chapter 7 Large and Fast: Exploiting Memory Hierarchy Bo Cheng.

Chapter 7 Large and Fast: Exploiting Memory Hierarchy Bo Cheng.
1 COMP 206: Computer Architecture and Implementation Montek Singh Mon., Nov. 3, 2003 Topic: Memory Hierarchy Design (HP3 Ch. 5) (Caches, Main Memory and.

1 COMP 206: Computer Architecture and Implementation Montek Singh Mon., Nov. 3, 2003 Topic: Memory Hierarchy Design (HP3 Ch. 5) (Caches, Main Memory and.
CS 61C L35 Caches IV / VM I (1) Garcia, Fall 2004 © UCB Andy Carle inst.eecs.berkeley.edu/~cs61c-ta inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures.

CS 61C L35 Caches IV / VM I (1) Garcia, Fall 2004 © UCB Andy Carle inst.eecs.berkeley.edu/~cs61c-ta inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures.
331 Lec20.1Fall 2003 14:332:331 Computer Architecture and Assembly Language Fall 2003 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152.

331 Lec20.1Fall :332:331 Computer Architecture and Assembly Language Fall 2003 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152.
ENGS 116 Lecture 121 Caches Vincent H. Berk Wednesday October 29 th, 2008 Reading for Friday: Sections C.1 – C.3 Article for Friday: Jouppi Reading for.

ENGS 116 Lecture 121 Caches Vincent H. Berk Wednesday October 29 th, 2008 Reading for Friday: Sections C.1 – C.3 Article for Friday: Jouppi Reading for.

Similar presentations

Ads by Google