2. Field-effect transistors ( FETs) MD.MASOOD AHMAD ASST.PROF ECE DEPT

3. Unipolar device i. e. operation depends on only one type of charge carriers (h or e) Voltage controlled Device (gate voltage controls drain current) Very high input impedance (  10 9 -10 12  ) Source and drain are interchangeable in most Low-frequency applications Low Voltage Low Current Operation is possible (Low-power consumption) Less Noisy as Compared to BJT No minority carrier storage (Turn off is faster) Self limiting device Very small in size, occupies very small space in Ics Low voltage low current operation is possible in MOSFETS Zero temperature drift of out put is possible Advantages of FET

4. Disadvantages of FET Transconductance is low and hence voltage gain is low They are more costly than junction transistors FET has relatively small gain bandwidth product

5. Types of Field Effect Transistors (The Classification)  JFET MOSFET (IGFET) n-Channel JFET p-Channel JFET n-Channel EMOSFET p-Channel EMOSFET Enhancement MOSFET Depletion MOSFET n-Channel DMOSFET p-Channel DMOSFET FET

6. Gate Drain Source SYMBOLS n-channel JFET Gate Drain Source p-channel JFET

7. Figure: n-Channel JFET. The Junction Field Effect Transistor (JFET)

8. Figure: n-Channel JFET and Biasing Circuit. Biasing the JFET

9. Figure: The nonconductive depletion region becomes broader with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.) Operation of JFET at Various Gate Bias Potentials

10. Junction FETs (JFETs) JFETs consists of a piece of high-resistivity semiconductor material (usually Si) which constitutes a channel for the majority carrier flow. Conducting semiconductor channel between two ohmic contacts – source & drain

11. Junction FETs (JFETs) The magnitude of this current is controlled by a voltage applied to a gate, which is a reverse-biased. The fundamental difference between JFET and BJT devices: when the JFET junction is reverse-biased the gate current is practically zero, whereas the base current of the BJT is always some value greater than zero.

12. Junction FETs JFET is a high-input resistance device, while the BJT is comparatively low. If the channel is doped with a donor impurity, n-type material is formed and the channel current will consist of electrons. If the channel is doped with an acceptor impurity, p-type material will be formed and the channel current will consist of holes. N-channel devices have greater conductivity than p- channel types, since electrons have higher mobility than do holes; thus n-channel JFETs are approximately twice as efficient conductors compared to their p-channel counterparts.

13. Basic structure of JFETs In addition to the channel, a JFET contains two ohmic contacts: the source and the drain. The JFET will conduct current equally well in either direction and the source and drain leads are usually interchangeable.

15. N-channel JFET This transistor is made by forming a channel of N-type material in a P-type substrate. Three wires are then connected to the device. One at each end of the channel. One connected to the substrate. In a sense, the device is a bit like a PN-junction diode, except that there are two wires connected to the N- type side.

16. PP + - DC Voltage Source + - + - N N Operation of a JFET Gate Drain Source

17. Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics. Non-saturation (Ohmic) Region: The drain current is given by Where, I DSS is the short circuit drain current, V P is the pinch off voltage Output or Drain (V D -I D ) Characteristics of n-JFET Saturation (or Pinchoff) Region:

18. Figure: If v DG exceeds the breakdown voltage V B, drain current increases rapidly. Break Down Region N-Channel JFET Characteristics and Breakdown

19. Figure: Typical drain characteristics of an n-channel JFET. V D -I D Characteristics of EMOS FET Saturation or Pinch off Reg. Locus of pts where

20. Figure: Transfer (or Mutual) Characteristics of n-Channel JFET I DSS V GS (off) =V P Transfer (Mutual) Characteristics of n-Channel JFET

21. JFET Transfer Curve This graph shows the value of I D for a given value of V GS

22. How JFET Function The gate is connected to the source. Since the pn junction is reverse- biased, little current will flow in the gate connection. The potential gradient established will form a depletion layer, where almost all the electrons present in the n-type channel will be swept away. The most depleted portion is in the high field between the G and the D, and the least- depleted area is between the G and the S.

23. Because the flow of current along the channel from the (+ve) drain to the (-ve) source is really a flow of free electrons from S to D in the n-type Si, the magnitude of this current will fall as more Si becomes depleted of free electrons. There is a limit to the drain current (I D ) which increased V DS can drive through the channel. This limiting current is known as I DSS (Drain-to-Source current with the gate shorted to the source). How JFET Function

24. The output characteristics of an n-channel JFET with the gate short-circuited to the source. The initial rise in I D is related to the buildup of the depletion layer as V DS increases. The curve approaches the level of the limiting current I DSS when I D begins to be pinched off. The physical meaning of this term leads to one definition of pinch-off voltage, V P, which is the value of V DS at which the maximum I DSS flows.

25. With a steady gate-source voltage of 1 V there is always 1 V across the wall of the channel at the source end. A drain-source voltage of 1 V means that there will be 2 V across the wall at the drain end. (The drain is ‘up’ 1V from the source potential and the gate is 1V ‘down’, hence the total difference is 2V.) The higher voltage difference at the drain end means that the electron channel is squeezed down a bit more at this end.

26. When the drain-source voltage is increased to 10V the voltage across the channel walls at the drain end increases to 11V, but remains just 1V at the source end. The field across the walls near the drain end is now a lot larger than at the source end. As a result the channel near the drain is squeezed down quite a lot.

27. Increasing the source-drain voltage to 20V squeezes down this end of the channel still more. As we increase this voltage we increase the electric field which drives electrons along the open part of the channel. However, also squeezes down the channel near the drain end. This reduction in the open channel width makes it harder for electrons to pass. As a result the drain-source current tends to remain constant when we increase the drain-source voltage.

28. Increasing V DS increases the widths of depletion layers, which penetrate more into channel and hence result in more channel narrowing toward the drain. The resistance of the n-channel, R AB therefore increases with V DS. The drain current: I DS = V DS /R AB I D versus V DS exhibits a sublinear behavior, see figure for V DS < 5V. The pinch-off voltage, V P is the magnitude of reverse bias needed across the p + n junction to make them just touch at the drain end. Since actual bias voltage across p + n junction at drain end is V GD, the pinch-off occur whenever: V GD = -V P.

30. Beyond V DS = V P, there is a short pinch-off channel of length, ℓ po. As V DS increases, most of additional voltage simply drops across ℓ po as this region is depleted of carriers and hence highly resistive. Voltage drop across channel length, L ch remain as V P. Beyond pinch-off then I D = V P /R AP (V DS >V P ).

31. What happen when negative voltage, says V GS = -2V, is applied to gate with respect to source (with V DS =0). The p + n junction are now reverse biased from the start, the channel is narrower, and channel resistance is now larger than in the V GS = 0 case.

32. The drain current that flows when a small V DS applied (Fig b) is now smaller than in V GS = 0 case. Applied V DS = 3 V to pinch-off the channel (Fig c). When V DS = 3V, V GD across p + n junction at drain end is -5V, which is –V P, so channel becomes pinch-off. Beyond pinch-off, I D is nearly saturated just as in the V GS =0 case. Pinch-off occurs at V DS = V DS(sat), V DS(sat) = V P +V GS, where V GS is –ve voltage (reducing V P ). For V DS >V DS(sat), I D becomes nearly saturated at value as I DS.

33. Beyond pinch-of, with –ve V GS, I DS is Where R AP (V GS ) is the effective resistance of the conducting n-channel from A to P, which depends on channel thickness and hence V GS. When V GS = -V P = -5V with V DS = 0, the two depletion layers touch over the entire channel length and the whole channel is closed. The channel said to be off.

36. There is a convenient relationship between I DS and V GS. Beyond pinch-off Where I DSS is drain current when V GS = 0 and V GS(off) is defined as –V P, that is gate-source voltage that just pinches off the channel. The pinch off voltage V P here is a +ve quantity because it was introduced through V DS(sat). V GS(off) however is negative, -V P.

39. I-V characteristics

41. JFET: I-V characteristics

42. The transconductance curve The process for plotting transconductance curve for a given JFET: Plot a point that corresponds to value of V GS(off). Plot a poit that corresponds to value of I DSS. Select 3 or more values of V GS between 0 V and V GS(off). For value of V GS, determine the corresponding value of I D from Plot the point from (3) and connect all the plotted point with a smooth curve.

44. JFET Biasing Circuits

47. Example: Example: Plot the dc bias line for the voltage- drivers biasing circuit

48. Figure n-Channel depletion MOSFET.

49. Figure Characteristic curves for an NMOS transistor.

50. Figure Drain current versus v GS in the saturation region for n-channel devices.

51. Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices, except for the directions of the arrowheads.

52. Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices, except for the directions of the arrowheads.

53. Figure Drain current versus v GS for several types of FETs. i D is referenced into the drain terminal for n-channel devices and out of the drain for p-channel devices.

54. Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.

55. Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.

56. Figure: For v GS < V to the pn junction between drain and body is reverse biased and i D =0.

57. Figure: For v GS >V to a channel of n-type material is induced in the region under the gate. As v GS increases, the channel becomes thicker. For small values of v DS,i D is proportional to v DS. The device behaves as a resistor whose value depends on v GS.

58. Figure: As v DS increases, the channel pinches down at the drain end and i D increases more slowly. Finally for v DS > v GS -V to, i D becomes constant.

59. Current-Voltage Relationship of n-EMOSFET Locus of points where

60. Figure: Drain characteristics

61. Figure: This circuit can be used to plot drain characteristics.

62. Figure: Simple NMOS amplifier circuit and Characteristics with load line.

63. Figure: Drain characteristics and load line

64. Figure v DS versus time for the circuit of Figure 5.13.

65. Figure Fixed- plus self-bias circuit.

66. Figure The more nearly horizontal bias line results in less change in the Q-point.

67. Figure Small-signal equivalent circuit for FETs.

68. Figure FET small-signal equivalent circuit that accounts for the dependence of i D on v DS.

69. Figure Determination of g m and r d. See Example 5.5.

70. Figure Common-source amplifier.

71. An Amplifier Circuit using MOSFET(CS Amp.)

72. Figure Small-signal equivalent circuit for the common-source amplifier. A small signal equivalent circuit of CS Amp.

73. Figure v o (t) and v in (t) versus time for the common-source amplifier of Figure 5.28.

74. Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.

75. Figure Source follower.

76. Figure Small-signal ac equivalent circuit for the source follower.

77. Figure Equivalent circuit used to find the output resistance of the source follower.

78. Figure Common-gate amplifier.

79. Small signal equivalent of common gate amplifier

80. Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.