1. Multiple Clock Domains (MCD) Arvind with Nirav Dave Computer Science & Artificial Intelligence Lab Massachusetts Institute of Technology

2. Plan Why Multiple Clock Domains 802.11a as an example How to represent multiple clocks in Bluespec MCD syntax Synchronizers Putting it all together November 10, 2009L20-2 http://csg.csail.mit.edu/Korea

3. Review: 802.11a Transmitter ControllerScramblerEncoderInterleaverMapper IFFT Cyclic Extend headers data 24 Uncoded bits Operates on 1-4 packets at a time Converts 1-4 packets into a single packet A lot of compute; n cycles/packet November 10, 2009 http://csg.csail.mit.edu/Korea L20-3 n depends on the IFFT implementation; for the superfolded version n  51

4. Analyzing Rates ControllerScramblerEncoder InterleaverMapper IFFT Cyclic Extend headers data Relative rates: f/52 f f/13 Can we run these parts at different speeds (i.e. clock frequencies) and have them interact safely? November 10, 2009 http://csg.csail.mit.edu/Korea L20-4

5. Power-Area tradeoff The power equation: P = ½ CV 2 f V and f are not independent; one can lower the f by lowering V – linear in some limited range Typically we run the whole circuit at one voltage but can run different parts at different frequencies We can often increase the area, i.e., exploit more parallelism, and lower the frequency (power) for the same performance November 10, 2009L20-5 http://csg.csail.mit.edu/Korea

6. IFFT for 802.11a The supefolded IFFT implementation uses the least area and the frequency is still low need to produce a symbol every 4seconds, i.e., at a frequency of 250KHz so the superfolded pipeline must run at 52x250KHz  13MHz November 10, 2009L20-6 http://csg.csail.mit.edu/Korea

7. Multiple Clock Domains may save power ControllerScramblerEncoder InterleaverMapper IFFT Cyclic Extend headers data Relative rates: f/52 f f/13 One would actually want to explore many relative frequency partitionings to determine the real area/power tradeoff November 10, 2009 http://csg.csail.mit.edu/Korea L20-7

8. Plan Why Multiple Clock Domains 802.11a as an example How to represent multiple clocks in Bluespec MCD syntax Synchronizers Putting it all together November 10, 2009L20-8 http://csg.csail.mit.edu/Korea

9. Associating circuit parts with a particular clock Two choices to split the design: Partition State Rules must operate in multiple domains Partition Rules State Elements must have methods in different clock domains November 10, 2009 http://csg.csail.mit.edu/Korea L20-9 It is very difficult to maintain rule atomicity with multi-clock rules. Therefore we would not examine “Partitioned State” approach further

10. Partitioning Rules Only touched by one domain Methods in red and green domains A method in each domain November 10, 2009 http://csg.csail.mit.edu/Korea L20-10

11. Handling Module Hierarchy Methods added to expose needed functionality November 10, 2009 http://csg.csail.mit.edu/Korea L20-11

12. We need a primitive MCD synchronizer: for example enq one on clock and deq/first/pop on another full/empty signals are conservative approximations may not be full when full signal is true We’ll discuss implementations later November 10, 2009L20-12 http://csg.csail.mit.edu/Korea FIFO

13. Back to the Transmitters ControllerScramblerEncoder InterleaverMapper IFFT Cyclic Extend headers data November 10, 2009 http://csg.csail.mit.edu/Korea L20-13

14. Domains in the Transmitter let controller <- mkController(); let scrambler <- mkScrambler_48(); let conv_encoder <- mkConvEncoder_24_48(); let interleaver <- mkInterleaver(); let mapper <- mkMapper_48_64(); let ifft <- mkIFFT_Pipe(); let cyc_extender <- mkCyclicExtender(); rule controller2scrambler(True); stitch(controller.getData,scrambler.fromControl); endrule … many such stitch rules … November 10, 2009 http://csg.csail.mit.edu/Korea L20-14 function Action stitch(ActionValue#(a) x, function Action f(a v)); action let v <- x; f(v); endaction endfunction These colors are just to remind us about domains

15. Coloring the rules? rule controller2scrambler(True); stitch(controller.getData, scrambler.fromControl); endrule rule scrambler2convEnc(True); stitch(scrambler.getData, conv_encoder.putData); endrule rule mapper2ifft(True); stitch(mapper.toIFFT, ifft.fromMapper); endrule All methods in the same domain Using different domains… November 10, 2009 http://csg.csail.mit.edu/Korea L20-15

16. Domain Crossing rule mapper2ifft(True); stitch(mapper.toIFFT, ifft.fromMapper); endrule inline stitch Different methods in an action are on different clocks – we need to change the clock domains rule mapper2ifft(True); let x <- mapper.toIFFT(); ifft.fromMapper(x) endrule November 10, 2009 http://csg.csail.mit.edu/Korea L20-16

17. Introduce a domain crossing module let m2ifftFF <- mkSyncFIFO(size,clkGreen, clkRed); November 10, 2009L20-17 http://csg.csail.mit.edu/Korea Many such synchronizers In real syntax, one clock value is passed implicitly

18. Fixing the Domain Crossing rule mapper2ifft(True); let x <- mapper.toIFFT(); ifft.fromMapper(x) endrule rule mapper2fifo(True); stitch(mapper.toIFFT, m2ifftFF.enq); endrule rule fifo2ifft(True); stitch(pop(m2ifftFF), ifft.fromMapper); endrule split November 10, 2009 http://csg.csail.mit.edu/Korea L20-18 let m2ifftFF <- mkSyncFIFO(size,clkGreen,clkRed); synchronizer syntax is not quite correct

19. Similarly for IFFT to CyclicExt let ifft2ceFF <- mkSyncFIFO(size,clkRed,clkBlue); rule ifft2ff(True); stitch(ifft.toCyclicExtender, ifft2ceFF.enq); endrule rule ff2cyclicExtender(True); stitch(pop(ifft2ceFF), cyc_extender.fromIFFT); endrule November 10, 2009 http://csg.csail.mit.edu/Korea L20-19 Now each rule is associated with exactly one clock domain!

20. Plan Why Multiple Clock Domains 802.11a as an example How to represent multiple clocks in Bluespec MCD syntax Synchronizers Putting it all together November 10, 2009L20-20 http://csg.csail.mit.edu/Korea

21. MCD Syntax in BSV: point of view Automate the simplest things Make it easy to do simple things Make it safe to do the more complicated things November 10, 2009 http://csg.csail.mit.edu/Korea L20-21

22. Clock Domains: The Simplest case Only one domain Need never be mentioned in BSV source Synthesized modules have an input port called CLK This is passed to all interior instantiated modules November 10, 2009 http://csg.csail.mit.edu/Korea L20-22

23. The Clock type Clock is an ordinary first-class type May be passed as parameter, returned as result of function, etc. Can make arrays of them, etc. Can test whether two clocks are equal Clock c1, c2; Clock c = (b ? c1 : c2); // b must be known at compile time November 10, 2009 http://csg.csail.mit.edu/Korea L20-23

24. Instantiating modules with non-default clocks Example: instantiating a register with explicit clock Modules can also take clocks as ordinary arguments, to be fed to interior module instantiations Clock c = … ; Reg# (Bool) b <- mkReg (True, clocked_by c); November 10, 2009 http://csg.csail.mit.edu/Korea L20-24

25. The clockOf() function May be applied to any BSV expression, and returns a value of type Clock If the expression is a constant, the result is the special value noClock noClock values can be used on in any domain The result is always well-defined Expressions for which it would not be well- defined are illegal November 10, 2009 http://csg.csail.mit.edu/Korea L20-25

26. The clockOf() function Example c, c1 and c2 are all equal Can be used interchangeably for all purposes Reg# (UInt# (17)) x <- mkReg (0, clocked_by c); let y = x + 2; Clock c1 = clockOf (x); Clock c2 = clockOf (y); November 10, 2009 http://csg.csail.mit.edu/Korea L20-26

27. A special clock Each module has a special “default” clock The default clock will be passed to any interior module instantiations (unless otherwise specified) It can be exposed in any module as follows: Clock c <- exposeCurrentClock; November 10, 2009 http://csg.csail.mit.edu/Korea L20-27

28. We actually want “gated” clocks Often, big circuits do not do useful work until some boolean condition holds We can save power by combining the boolean condition with the clock (i.e. clock gating) November 10, 2009L20-28 http://csg.csail.mit.edu/Korea Big Circuit clk input g g f f gating signal to be continued