1. Front-end Electronic for the CALICE ECAL Physic Prototype Christophe de La Taille Julien Fleury Gisèle Martin-Chassard Front-end Electronic for the CALICE ECAL Physic Prototype Christophe de La Taille Julien Fleury Gisèle Martin-Chassard

2. I – FLC_PHY3 : front-end chip for the ECAL physic prototype

3. I-a – FLC_PHY3 quick description FLC_PHY3 is a 18-channels front-end chip designed to read out the 36-channels Si wafers of the CALICE Si-W calorimeter physic prototype 1000 chips has been produced in 2004 to read out the 9720 channels of the prototype.

4. I-b – FLC_PHY3 - 1 channel overview Amp OPA MUX out Gain=1 MUX out Gain=10 1 channel 4 bits for gain selection Gain from 0.3 to 5 V/pC Gain selected by slow control Multi-gain charge preamp Gain 1 and gain 10 Work in parallel to select gain a posteriori Dual shaper & track and hold

5. Linearity curves (sweeping Cf / G1) Residuals (Cf=1.6pF / G1) Within ‰ linearity : Q IN MAX = 6.04 pC (900 MIP) @Cf=3pF Q IN MAX = 3.27 pC (500 MIP) @Cf=1.6pF Q IN MAX = 0.41 pC (60 MIP) @Cf=0.2pF Measured input charge swing I-c – FLC_PHY3 - Linearity Performance  Unit gain (C d =68pF, C f =1.6pF): 12 bit Noise = 0.1MIP  Saturation=500MIP  Dual gain (Cd=68pF, Cf=3pF): 13 bit Noise = 0.1MIP  Saturation=900MIP  Target (0.1-3000 MIP): 15 bit Will be reached with C f =10pF and bi-gain 12 bit readout Dynamic range

6. I-d – FLC_PHY3 - uniformity Gain uniformity for gain 1Peaking time uniformity for gain 1 Pedestal uniformity for gain 1 Gain696 mV ± 2.5% RMS Peaking time189ns ± 1% RMS Pedestal -3.7 ± 4.8mV RMS Gain 1 Uniformity @ Cf=1.6pF

7. I-d – FLC_PHY3 - uniformity (contd) Gain6294 mV ± 2.9% RMS Peaking time174ns ± 1% RMS Pedestal -3.7 ± 8.3mV RMS Gain 10 Uniformity @ Cf=1.6pF Gain uniformity for gain 10 Pedestal uniformity for gain 10 Peaking time uniformity for gain 10

8. I-e – FLC_PHY3 - Noise Performance ENC measurement and fit (Cf=1.6pF) Noise Series : e n = 1.6nV/√Hz Detector + line capacitance on physic proto : 70 pF  ENC : 4000 e - ( 1/10 MIP)  Ouput noise : 500 μV RMS Crosstalk Below 1 ‰ with gain 1 shaping Below 2 ‰ with gain 10 shaping

9. II – PCB design : go thinner and reduce the moliere radius

10. II-a – PCB design : the physic prototype 6 active wafers Made of 36 silicon PIN diodes  216 channels per board Each diode is a 1cm² square 12 FLC_PHY3 front-end chip 18 channels per chip 13 bit dynamic range 2 calibration switches chips 6 calibration channels per chip 18 diodes per calibration channel Line buffers To DAQ part Differential 14 layers 2.1 mm thick Made in korea

11. II-a – PCB design : the physic prototype (contd) Expectations :  Validation of the detector physic principle -Fast R&D (10,000-channels detector produced in 2 years) -Conservative design to fit the schedule -Starting point for technologic R&D

12. II-b – PCB_FEV3: a new PCB toward final detector - Compatible with ECAL physics proto - 2 active wafer spots (with epitaxial capacitance) - 8 temperature measurement points - FE Chips on back of PCB - 640 µm thick - Back from assembling : March, 7 PCB features - Validation of wafer epitaxial capacitance Performance, Gluing, … - Lower noise (to be measured) Due to shorter lines - Better uniformity (to be measured) Due to better voltage references - FE chip in EM shower ? Measurement expectations

13. II-c – PCB design : a new PCB toward final detector 1.5m Technologic prototype Physic prototype slab 0.3m Crucial point : industrialization See talk by Jean-Claude Brient

14. II-c – PCB design : a new PCB toward final detector Wafer (525µm) PCB (2.1mm) Tungsten Physic Prototype Slab 3300µm diodes+ FE electronic Pictures II-c : M. Anduze Technologic Prototype Slab FE chip (1mm) Wafer (500µm) PCB (600µm) 1750µm diodes+ FE electronic -47% thickness See talk by Jean-Claude Brient

15. II-d – A techno prototype within 3 years ? Module 0 - The two first stack of a module - Real length (1.5m) - 30 layers Module 0 - The two first stack of a module - Real length (1.5m) - 30 layers EUDET : EUropean DETector  Waiting for commitee answer… European funding asked - 100,000 channels - 3000 MIP dynamic range -Auto-trigger -On-chip Zero suppress -On-chip analog to digital conversion  Performance of the final detector ECAL – MODULE ZERO FLC_FEV3 : Just presented FLC_PHY4 : See next talk by C. de La Taille Starting points

16. III-a – Conclusion FLCPHY3 chip fulfills FLC Wsi testbeam prototype –Low Noise : 4000e- = 0.1 MIP –Maximum signal : 500 MIPs –Linearity : 0.1%, crosstalk 0.1% –Low pedestal dispersion : 4.8mV rms = 1 MIP –Can fit other detectors (variable gain 0.2-3pF, bi-gain G1-G10 shaper) PCB design is going on to achieve minimum thickness and best industrialization –FLC_FEV3 designed, to be tested –FLC_FEV4 (power switching, digital output) embedding FLC_PHY4, end of 2005 Next steps for front-end ASIC : FLC_PHY4 –Low power developments for technological prototype –New chip in CMOS 0.35µm with Idle mode –Trying to integrate the ADC… See next talk by Christophe de La Taille

17. III-b – Questions